Three-stage Clos-network Switch Research Articles

TRIDENT: A Load-Balancing Clos-Network Packet Switch With Queues Between Input and Central Stages and In-Order Forwarding

We propose a three-stage load balancing packet switch and its configuration scheme. The input- and central-stage switches are bufferless crossbars, and the output-stage switches are buffered crossbars. We call this switch ThRee-stage Clos-network swItch with queues at the middle stage and DEtermiNisTic scheduling (TRIDENT), and the switch is cell based. The proposed configuration scheme uses predetermined and periodic interconnection patterns in the input and central modules to load-balance and route traffic, therefore, it has low configuration complexity. The operation of the switch includes a mechanism applied at input and output modules to forward cells in sequence. TRIDENT achieves 100% throughput under uniform and nonuniform admissible traffic with independent and identical distributions (i.i.d.). The switch achieves this high performance using a low-complexity architecture while performing in-sequence forwarding and no central-stage expansion or memory speedup. We analyze the operations the configuration mechanisms perform on the traffic traversing the switch. We use this analysis to prove that the switch achieves 100% through under i.i.d. traffic. We also show that the switch forward cells in-sequence. We present a simulation analysis as a practical demonstration of the switch performance under uniform and nonuniform i.i.d. traffic.

Performance Analysis of Clos-Network Packet Switch with Virtual Output Queues

A three-stage Clos-network switch with input queues is attractive for practical implementation of a large-capacity packet switch. A scheme that configures the first, second, and third stages in that sequence by performing iterative matchings based on random selections is called the staged random scheduling scheme. Despite the usefulness of such a switch, the literature provides no analytical formula that can accurately calculate its throughput. This paper develops a formula to calculate the throughput analysis of the staged random scheduling scheme for one and multiple iterations used in an input-queued Clos-network switch under uniform traffic. This formula can be used to verify simulation models for very large switches. The introduced derivation considers the processes of the selection scheme at each stage of the switch. The derived formula is used in numerical evaluations to show the throughput of large switch sizes. The results show that the staged random scheduling scheme with multiple iterations for a Clos-network switch with VOQs without internal expansion approaches 100% throughput under uniform traffic. Furthermore, evaluations of the derived formulas are used in a practical application to estimate the number of iterations required to achieve 99% throughput for a given switch size. In addition, the staged random scheduling scheme in an input-queued Clos-network switch is modeled and simulated to compare throughput estimations to those obtained with the derived formulas. The simulation results support the correctness of the derived formulas.

THREE-STAGE CLOS-NETWORK SWITCH ARCHITECTURE WITH BUFFERED CENTER STAGE FOR MULTI-CLASS TRAFFIC

Memory-space-memory (MSM) arrangement is a popular architecture to implement three-stage Clos-network switches with distributed arbitration. The scalability of this architecture, however, is limited by the round-trip communication delay between the first and the second stages. Moreover, virtual output queue does not completely remove the blocking in the buffered modules under multi-class traffic. In this paper, we propose a competition-free memory–memory–memory (CFM3) switch which is a three-stage Clos-network switch with buffered center stage. The CFM3 deploys buffered modules in all stages to simplify communication between stages. To reduce the blocking, each module is equipped with a set of buffers fully separated according to the destinations, classes of packets and the input ports of the module. Despite the buffered center stage, CFM3 is free from reordering problem due to simple control mechanism. Simulation result shows the delay of the proposed CFM3 switch closely approaches that of the ideal Output Queued switch under multi-class traffic when strict priority policy popularly used for class-based switch is deployed. The CFM3 achieves 100% throughput under uniformly distributed four-class traffic with strict priority policy while traditional MSM switch records about 77% throughput.

Petastar: a petabit photonic packet switch

This paper presents a new petabit photonic packet switch architecture, called PetaStar. Using a new multidimensional photonic multiplexing scheme that includes space, time, wavelength, and subcarrier domains, PetaStar is based on a three-stage Clos-network photonic switch fabric to provide scalable large-dimension switch interconnections with nanosecond reconfiguration speed. Packet buffering is implemented electronically at the input and output port controllers, allowing the central photonic switch fabric to transport high-speed optical signals without electrical-to-optical conversion. Optical time-division multiplexing technology further scales port speed beyond electronic speed up to 160 Gb/s to minimize the fiber connections. To solve output port contention and internal blocking in the three-stage Clos-network switch, we present a new matching scheme, called c-MAC, a concurrent matching algorithm for Clos-network switches. It is highly distributed such that the input-output matching and routing-path finding are concurrently performed by scheduling modules. One feasible architecture for the c-MAC scheme, where a crosspoint switch is used to provide the interconnections between the arbitration modules, is also proposed. With the c-MAC scheme, and an internal speedup of 1.5, PetaStar with a switch size of 6400 /spl times/ 6400 and total capacity of 1.024 petabit/s can be achieved at a throughput close to 100% under various traffic conditions.