Three-phase Seven-level Inverter Research Articles

Eighteen-Step Inverter: A Low-Loss Three-Phase Inverter for Low-Cost Standalone Applications

In this article, a new three-phase seven-level inverter is proposed with a new switching algorithm. This algorithm has eighteen switching steps. The switching algorithm is implemented on a topology, which consists of three legs and each leg has four switches. The switching frequency for six switches is the same as output wave frequency. The proposed algorithm results in lower switching losses, higher efficiency, and lower number of switches. This inverter has low cost and low volume, and is especially suitable for standalone applications. In addition, a modified pulsewidth modulation (PWM)-based version is proposed for eighteen-step switching algorithm to reduce the filter size and increase the controllability of the output waveform. Simulation and experimental results demonstrate good performance of the proposed inverter.

A Seven-Level VSI With a Front-End Cascaded Three-Level Inverter and Flying-Capacitor-Fed H-Bridge

Multilevel inverters (MLIs) are playing a pivotal role in the power sector with potential applications, such as interfacing renewable energy sources with the grid and several industrial drive applications. MLIs with a smaller number of switching devices are more promising due to their compact size, reduced cost, and higher efficiency compared with their traditional counterparts. This paper, therefore, presents a new three-phase seven-level inverter. This topology is a combination of two cascade-connected two-level voltage-source inverters (VSIs) and H-bridge cells with flying capacitors (FCs). This paper presents the operating principle and the balancing technique for the dc-link capacitors and FCs. The generation of various output voltage levels and the limitation of the sinusoidal pulsewidth modulation control for FC voltage balancing is also presented. The number of components in the proposed circuit configuration and their voltage ratings are considerably lower compared with the recently proposed topologies. The behavior of the proposed circuit configuration is first assessed with simulation studies and is then tested with a laboratory prototype. The simulation and experimental results validate the effectiveness of the proposed topology and the voltage balancing technique.

Multi-level model predictive controller with satisfactory optimization for multi-level converters

In this paper, a simplified Model Predictive Control (MPC) technique is proposed for a hybrid three-phase seven-level inverter based on Active Neutral Point Clamped (ANPC) converter cascaded to an H-bridge with a flying capacitor. This converter has the ability to balance switching losses, to withstand high voltages and to operate with fewer semiconductors. It is interesting for high-voltage and high-quality exigent applications. By introducing a trade-off relation between control actions reduction and the flying capacitor charge, the designed controller can maintain the capacitor voltage with less number of switching states. This reduces computations, eliminates common mode voltage, shortens optimization time, and improves output current quality. Moreover, in this work, a multilevel MPC architecture is presented, where the MPC approach is divided into two-level units. The major level unit is composed of separated sub-MPC controllers for each phase that track the three-phase current references, while the second level unit is composed of only one MPC model that balances the capacitor charge at its nominal values. An additional control design of the major level MPC is presented, where a satisfactory optimization of common mode voltage is used instead of weighting factor in the cost function, which simplifies the control approach, and solves the problem of selecting the right weighting factors. Simulation analysis shows the effectiveness of the proposed methods.

Selective harmonic elimination in multilevel inverter using hybrid APSO algorithm

This study presents selective harmonic elimination pulse width modulation technique-based hybrid asynchronous PSO-Newton-Raphson (APSO-NR) algorithm for the elimination of undesired harmonics in cascaded H-bridge multilevel inverter. The proposed algorithm is applicable to all levels of MLI having equal and non-equal DC sources. In the proposed method, ring topology-based APSO algorithm is hybrid with NR method. APSO worked as a global search technique and NR is used for the refinement of best solutions. APSO-NR is applied to the seven-level inverter to eliminate fifth and seventh harmonics. In simulations, the performance of the proposed algorithm is compared with genetic algorithm, bee algorithm and particle swarm optimisation. The results proved that the proposed algorithm is efficient, and gives more precise firing angles in less number of iterations with high capability of tackling local optima. For the 48% of modulation index range, APSO-NR minimised the fitness function value lower than (10 -25 ). The proposed algorithm is validated through the experimental implementation of the three-phase seven-level inverter.

Compensation of DC link voltage variation of a multilevel series-connected H-bridge inverter

The phase voltages of a series-connected H-bridge multilevel inverter are formed from galvanically isolated secondaries of complicated transformer. The reactive energy of a reactive load flowing back to the DC links is not transferred to other phases the same way as is in two-level inverters. Therefore the DC link voltages in multilevel inverters fluctuate under load and cannot be considered constant. Voltage fluctuation causes several problems including erroneous voltage vector production and undesired harmonics to voltage and current. A simple compensation method for such a DC link voltage fluctuation in series-connected multilevel inverters is proposed. The method is shown to be applicable to both space vector modulation and duty-cycle modulation schemes. The algorithm also includes circulation of the modules to ensure equal loading of different DC links. The proposed method was simulated using the parameters of a 3 kV three-phase seven-level inverter. Laboratory measurements with a 100 kVA inverter also verify the operation. The simulations and test results show the algorithm to fix unideal voltages to correspond the demanded reference. Also DC link voltages remain very well in balance, because of the use of module circulation.

Harmonic elimination in diode-clamped multilevel inverter using evolutionary algorithms

This paper describes two evolutionary algorithms for the optimized harmonic stepped–waveform technique. Genetic algorithms and particle swarm optimization are applied to compute the switching angles in a three-phase seven-level inverter to produce the required fundamental voltage while, at the same time, specified harmonics are eliminated. Furthermore, these algorithms are also used to solve the starting point problem of the Newton-Raphson conventional method. This combination provides a very effective method for the harmonic elimination technique. This strategy is useful for different structures of seven-level inverters. The diode-clamped topology is considered in this study.