Three-level Power Factor Correction Research Articles

A Novel Interleaved Parallel Cascaded Three-Level PFC With Low Inductance Volt-Second and Low Common-Mode Noise

Interleaved parallel cascaded multilevel technology is an attractive approach for converters to achieve high efficiency, high-power density, and high modularity. In this letter, a novel single-phase interleaved parallel cascaded three-level (IPC-TL) power factor correction (PFC) converter is proposed. It is formed by cascading two interleaved parallel totem-pole PFC cells. The proposed topology exhibits the merits of lower inductance volt-second and inductor current ripples, lower common-mode noise, and lower control cost, compared with the traditional IPC-TL topology. A laboratory-scale experimental prototype is developed to verify the effectiveness of the proposed topology.

High-Power-Density Single-Phase Three-Level Flying-Capacitor Buck PFC Rectifier

Active pulsating power buffering (PPB) is an effective technique to reduce the energy storage requirement of a single-phase power-factor-correction (PFC) rectifier. Existing single-phase solutions with active PPB, however, generally suffer from high voltage stresses, leading to increased power losses as well as the need for high-voltage-rating semiconductor switches. Previous works have been focusing on two-level switching converter configurations, and thus have failed to address the high-voltage-stress problem. In this paper, a single-phase three-level flying-capacitor PFC rectifier with PPB-embedded switching is proposed. The flying capacitor not only clamps the voltage stresses of all power devices but also functions as a PPB capacitor. The operating principles, control methods, and design guidelines are detailed and the feasibility of the proposed converter is verified through a 48-W (48-V/1-A) hardware prototype. The proposed rectifier is shown to achieve nearly 50% reduction of the voltage stresses, 72% reduction of the buffering capacitor's volume, and 23.8% reduction of the magnetic core size, as compared to a state-of-the-art two-level solution recently proposed. This new approach of formulating single-phase PFC rectifiers with active PPB could dramatically boost the system's efficiency and power density whilst reducing cost.

Design and Control of a 13.2 kV/10 kVA Single-Phase Solid-State-Transformer with 1.7 kV SiC Devices

This paper describes the power stage design, control, and performance evaluation of a 13.2 kV/10 kVA solid-state-transformer (SST) for a power distribution system. The proposed SST consists of 10 modules where each individual module contains a unidirectional three-level power factor correction (PFC) converter for the active-front-end (AFE) stage and an LLC resonant converter for the isolated DC-DC stage. The operating principles of the converters are analyzed and the modulation and the control schemes for the entire module are described in detail. The DC-link voltage imbalance is also less than other SST topologies due to the low number of uncontrollable switching states. In order to simplify the control of the power stage, a modulation strategy for the AFE stage is proposed, and the modulation frequency of the LLC converter is also fixed. In addition, a compensation algorithm is suggested to eliminate the current measurement offset in the AFE stage. The proposed SST achieves the unity power factor at the input AC current regardless of the reactive or nonlinear load and a low voltage regulation at the AC output. In order to verify the effectiveness of the SST, the 13.2 kV/10 kV SST prototype is built and tested. Both the simulation and the experimental results under actual 13.2 kV line show the excellent performance of the proposed SST scheme.

High-Efficiency Bridgeless Three-Level Power Factor Correction Rectifier

A high-efficiency bridgeless three-level power factor correction (PFC) rectifier is proposed. The circuit configuration of the proposed rectifier consists of four metal oxide semiconductor field-effect transistor (MOSFET) switches, and the reverse recovery problems of the switches are eliminated. Also, the proposed rectifier with three voltage levels reduces the power losses, harmonic components, voltage ratings, and electromagnetic interference. To control the grid current and the output voltage effectively, a feed-forward nominal voltage compensator with the mode selector is developed; by presetting the operating point of the grid voltage, this compensator improves the control environment. Thus, the proposed three-level PFC rectifier with developed control algorithm provides high power quality and high efficiency of 99.05%. Experimental results based on a 1-kW prototype are provided to evaluate its performance and verify the analysis.

Modified Interleaved Current Sensorless Control for Three-Level Boost PFC Converter With Considering Voltage Imbalance and Zero-Crossing Current Distortion

The three-level boost power factor correction (PFC) converter has advantages of lower inductor current ripple and lower switch withstanding voltage compared with the boost PFC converter. Interleaved pulsewidth modulation had been used in the multiphase boost PFC converter. In the literature, interleaved current sensorless control (ICSC) for the multiphase boost PFC converters had been proposed. In this paper, the behavior of the three-level boost PFC converter is first analyzed. The results show that three-level converter has the same average equation as the interleaved boost PFC converter. Then, ICSC is modified for the three-level boost PFC converter with considering the voltage imbalance and the zero-crossing current distortion. The proposed modified ICSC (MICSC) is implemented in a field-programmable gate array board. Simulation results and experimental results are also provided to validate the proposed MICSC.

Analysis on the slow-scale bifurcation behaviors of one-cycle-controlled three-level Boost power factor correction converter

In this paper, the slow-scale bifurcation phenomenon of the one-cycle-controlled three-level Boost power factor correction (PFC) converter is studied in depth, aiming at analyzing the influence of main circuit parameters on the stability of the system based on Floquet multiplier method. Firstly, the working principle of the circuit is analyzed, and a simplified model is derived according to the power balance principle. The periodic solutions are investigated using the harmonic balance method, and its stability is studied by the Floquet theory. By calculating the Floquet multiplier, the influence of the voltage compensator resistor Rvf on the slow-scale behavior of the system is analyzed. The simulation result verifies the correctness of the simplified model and theoratical analysis. Finally, the stability boundary composed of filter capacitor C and load resistor R as well as feedback resistor Rvf and capacitor Cvf is calculated and simulated under certain conditions. The circuit simulation result is consistent with the theoretical calculation. The results show that the correct choice of circuit parameters of three-level Boost PFC converter is very important for achieving its stable operation and improving the power factor.

Analysis, design and control of single‐phase three‐level power factor correction rectifier fed switched reluctance motor drive

In this study, a single-phase three-level power factor correction (PFC) rectifier fed switched reluctance motor (SRM) drive is proposed for improving the power quality at ac mains. The asymmetry in the dc-link capacitors voltages of the midpoint converter fed SRM drive is improved by using a single-phase three-level PFC rectifier. This PFC rectifier configuration uses two active semiconductor switches, an inductor and operates as a boost PFC rectifier. The proposed single-phase three-level PFC rectifier fed SRM drive is designed, modelled and its performance is simulated in MATLAB/Simulink. The simulated performance of the proposed single-phase three-level PFC rectifier fed SRM drive is experimentally validated for dc-link capacitors voltage balancing and power quality improvement.

Single phase three-level power factor correction circuit with passive lossless snubber

Multilevel conversion techniques, power factor correction (PFC) techniques and soft switching techniques are the three research hot points of power electronics. The paper proposes a single phase three-level PFC circuit with passive lossless snubbers which embodies these trends. Firstly, the three-level buck and boost topologies are derived from one bridge leg of the traditional diode clamped three-level inverters. Then, a single phase three-level PFC circuit is presented based on the three-level boost topology, and the principle and implementation approaches of the three-level PFC circuit are described. To realize the soft switching of the main switches and freewheeling diodes, two passive lossless snubber cells are added to the circuit. The operating principle and design considerations of the new circuit are discussed in detail. Finally, a 2 kW prototype of the single phase three-level PFC with the passive lossless snubber is built and tested. The simulated and experimental results indicate that the proposed circuit can realize the function of three-level PFC, increase system efficiency and have no over-voltage stresses on main power switches. Moreover, the power factor of the proposed circuit with the passive lossless snubber is higher than that of the circuit without the snubber.