Thin High-k Dielectrics Research Articles

(Invited) HfO2/Al2O3 Nanolaminate on Si0.7Ge0.3(100) Surface by Thermal Atomic Layer Deposition

To integrate Silicon-Germanium (SiGe) into future CMOS devices, it is essential to deposit very thin high-k dielectrics on SiGe surfaces with low density interfacial defects. In this study, Al2O3/HfO2 nanolaminate (HfO2 layers incorporated with Al2O3 monolayers) gate stacks were deposited by atomic layer deposition (ALD) using HfCl4 and H2O precursors. Electrical properties of the interfaces were quantified by capacitance-voltage (C–V) spectroscopy. Interfaces of nanolaminate stacks were found to have 2x smaller density of interface traps (Dit) than pure HfO2 gate stacks. Cross sectional TEM with Energy-dispersive X-ray spectroscopy (EDS) showed that an SiOx rich interlayer was formed between the nanolaminate and the Si0.7Ge0.3(001) substrate. The SiOx interlayer contains almost no Ge indicating that the HfCl4/TMA nanolaminate deposition reduced the GeOx in the interface. Furthermore, the SiGe surface was enriched in Ge from 30% to ~70% consistent with the HfCl4/TMA nanolaminate process reducing and redepositing Ge on the SiGe surface.

Impact of thin high-k dielectrics and gate metals on RF characteristics of 3D double gate junctionless transistor

RF performance of 3D double gate junctionless transistor (JLT) is investigated considering thin high-k dielectrics and gate metals. The 3D double gate junctionless transistor (JLT) with 20nm gate length is designed and simulated in order to study the RF parameters such as transconductance, transconductance generation factor, output conductance and resistance, intrinsic capacitance, cut-off frequency, early voltage, and intrinsic gain. High-k dielectric gate oxide and gate metals have effect on the DC characteristics of JLT. However, in order to evaluate the impact of high-k gate dielectrics on the RF performance of the device, SiO2, Si3N4, HfO2 dielectrics are considered and compared their performances. Furthermore, the effect of various gate metals on RF performances of the device is also discussed. Gate oxide with higher-k value improves the transconductance, output conductance, and intrinsic gain of the device. While, gate metal with lower work function exhibits better RF characteristics in JLT, application of different high-k dielectrics and gate metal have no improvement in cut-off frequency. The investigation gives an idea to optimize the RF performance of the device using suitable gate dielectric and gate metal. This investigation helps to create an opportunity for the junctionless transistor to realize high performances RF circuits.

Applicability of molecular beam deposition for the growth of high-k oxides

Following the demand of replacing conventional dielectrics in the semiconductor industry, a material screening for new high-k dielectrics is necessary. In this article, the molecular beam deposition is presented as a versatile and valuable tool for growing dielectric films. ZrO2 was chosen as an example to demonstrate the capability of molecular beam deposition to grow thin high-k dielectrics in a metal-insulator-metal stack. A k-value from 21 to 26 could be achieved for as-grown films. This could be improved even further up to 30 by performing postdepositions anneals that result in a capacitance equivalent thickness of 1.5 nm at a leakage current density of 1.5×10−7 A/cm2. In addition, the crystallization behavior of ZrO2 was investigated.

UHV CAFM characterization of high-k dielectrics: Effect of the technique resolution on the pre- and post-breakdown electrical measurements

In this work, a Conductive Atomic Force Microscopy (CAFM) working in contact mode has been used to compare the measured electrical properties and breakdown (BD) on ultra thin high-k dielectrics, when different environmental conditions are used. In particular, the effect of the environment on the conductivity measurements, the lateral resolution in current images and the lateral propagation of the BD event will be analyzed in air, dry nitrogen (N 2) and Ultra High Vacuum (UHV).

Small Signal Response of Inversion Layers in High Mobility In0.53Ga0.47As MOSFETs Made with Thin High-k Dielectrics

Ultra-high mobility compound semiconductor-based MOSFETs and quantum-well FETs could enable the next generation of logic transistors operating at low supply voltages since these materials exhibit excellent electron transport properties. While the long channel In0.53Ga0.47As MOSFET characteristics exhibit promising characteristics with unpinned Fermi level at the InGaAs-dielectric interface, the high field channel mobility as well as sub-threshold characteristics needs further improvement. There could be contribution from one or several potential scattering processes to cause mobility degradation in surface channel In0.53Ga0.47As MOSFETs such as interface roughness, remote or local optical phonon scattering and remote Coulomb scattering due to charges in the gate oxide. In this work, we present a comprehensive equivalent circuit model that accurately models the experimental small signal response of inversion layers in In0.53Ga0.47As MOSFETs fabricated with LaAlO3 gate dielectric and enables accurate extraction of effective channel mobility. Temperature dependent measurements allow us to identity the various scattering mechanisms.

Small Signal Response of Inversion Layers in High Mobility In0.53Ga0.47As MOSFETs Made with Thin High-k Dielectrics

not Available.

Suppression of parasitic electron injection in silicon-oxide-nitride-oxide-silicon-type memory cells using high-k capping layers

In this article the application of thin high-k dielectrics as capping layers on oxide/nitride/oxide memory stacks with respect to suppression of electron injection from the gate electrode during erase operation is investigated. The authors demonstrate that hafnium silicate layers, with a dielectric constant of 17, as thin as 1nm of physical thickness can clearly reduce electron injection and thereby prevent erase saturation. In theory, tunneling currents will be more strongly suppressed with increasing k values when keeping the equivalent oxide thickness constant. Therefore, the prevention of erase saturation will be further improved. However, titanium oxide as capping layer, which has a dielectric constant of 60, exhibits inferior erase performance due to a strong electron injection by field-enhanced thermal emission of electrons. This Poole-Frenkel conduction mechanism takes place along trapping sites 0.32eV below the conduction band in the titanium dioxide. While the application of high-k materials can efficiently suppress erase saturation due to tunneling currents, this effect can be diminished by leakage currents along shallow trapping sites which occur in high-k dielectrics.

Tunneling atomic-force microscopy as a highly sensitive mapping tool for the characterization of film morphology in thin high-k dielectrics

High-k dielectric layers (HfSixOy and ZrO2) with different film morphologies were investigated by tunneling atomic-force microscopy (TUNA). Different current distributions were observed for amorphous and nanocrystalline films by analyzing TUNA current maps. This even holds for crystalline layers where highly resolved atomic-force microscopy cannot detect any crystalline structures. However, TUNA enables the determination of morphology in terms of differences in current densities between nanocrystalline grains and their boundaries. The film morphologies were proven by high-resolution transmission electron microscopy. The investigations show TUNA as powerful current mapping tool for the characterization of morphology in thin high-k films on a nanoscale.