Bottom Oxide Thickness Research Articles

Investigation of 4H-SiC UMOSFET Architectures for High Voltage and High Speed Power Switching Applications

A comparative TCAD (Technology Computer Aided Design) simulation study of various 4H-SiC trench gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (or U-shaped trench gate MOSFET abbreviated for UMOSFET) architectures for high voltage and high-speed switching applications is reported. The DC (Direct Current) and AC (Alternating Current) characteristics of the different trench gate structures are investigated. Particularly, compared to conventional 4H-SiC UMOSFETs, the breakdown voltage of the UMOSFET having a p-type implanted bottom shield is increased by 44%. However, due to the extra JFET (Junction Field Effect Transistor) region, the specific on resistance also increases by 6%. Furthermore, under 1000 V drain bias, the peak electric field at the bottom oxide of the shielded trench gate is below 0.3 MV/cm. In contrast, the peak electric field of conventional UMOSFETs can be as high as 8 MV/cm, which might cause reliability issues. On the other hand, when the bottom oxide thickness of the trench gate is increased, the UMOSFET exhibits 22% less total gate charge, leading to 76% and 71% shorter switching delay time, compared to conventional UMOSFETs and bottom shield UMOSFETs, respectively. As revealed by the simulation results, the UMOSFETs with the p-type implanted bottom shield or thick bottom oxide are advantageous for high voltage and high-speed power switching applications.

Relationship of drain induced barrier lowering and top/bottom gate oxide thickness in asymmetric junctionless double gate MOSFET

The relationship of drain induced barrier lowering (DIBL) phenomenon and channel length, silicon thickness, and thicknesses of top and bottom gate oxide films is derived for asymmetric junctionless double gate (JLDG) MOSFETs. The characteristics between the drain current and the gate voltage is derived by using the potential distribution model to propose in this paper. In this case, the threshold voltage is defined as the corresponding gate voltage when the drain current is (W/L) × 10-7 A, and the DIBL representing the change in the threshold voltage with respect to the drain voltage is obtained. As a result, we observe the DIBL is proportional to the negative third power of the channel length and the second power of the silicon thickness and linearly proportional to the geometric mean of the top and bottom gate oxide thicknesses, and derive a relation such as DIBL =25.15ηL_g^(-3) t_si^2 √(t_ox1∙t_ox2 ), where η is a static feedback coefficients between 0 and 1. The η is found to be between 0.5 and 1.0 in this model. The DIBL model of this paper has been observed to be in good agreement with the result of other paper, so it can be used in circuit simulation such as SPICE.

Analytical modelling and verification of potential profile of DG JLFET with and without stack oxide

ABSTRACT In this paper, a physically based two-dimensional analytical model of potential profile is proposed for both symmetric and asymmetric p-type-doped Double Gate Junctionless Field Effect Transistors (DG JLFETs). The proposed model keeps its validity in the subthreshold region. In order to establish the model, 2-D Poisson’s equation is solved in the channel region while assuming cubic potential distribution along the channel region. We also propose a 2-D analytical model of symmetric Double Gate Stack-Oxide Junctionless Field Effect Transistors (DGS JLFETs). In order to check out the validity of our proposed model, we have used SILVACO ATLAS simulator. Comparison of potential distribution is made between different structures. Between symmetric and asymmetric structures, symmetric structure shows better potential profile as they have shown higher potential distribution in channel region. But when DG JLFET is compared with DGS JLFET, we find better potential profile distribution in DGS JLFET. Important performance parameters like Ion/Ioff ratio, SS, DIBL, Threshold Voltage, I–V characteristics for different structures are found out and compared among them. Asymmetric structure with same electrode materials in both gates but having lower bottom gate oxide thickness showed better performances like higher Ion/Ioff ratio, lower SS, less DIBL compared to other DG JLFETs with and without stack oxide.

Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET

Threshold voltage roll-off is analyzed for sub-10 nm asymmetric double gate (DG) MOSFET. Even asymmetric DGMOSFET will increase threshold voltage roll-off in sub-10 nm channel length because of short channel effects due to the increase of tunneling current, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top and bottom oxide thicknesses will affect the threshold voltage roll-off. To analyze this, <em>thermal</em><em> </em>emission current and tunneling current have been calculated, and threshold voltage roll-off by the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off is more influenced by silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage. Therefore, it is possible to reduce the leakage current of the top gate related with threshold voltage by increasing the thickness of the top gate oxide while maintaining the same threshold voltage.

Threshold Voltage Roll-off by Structural Parameters for Sub-10 nm Asymmetric Double Gate MOSFET

This study is to analyze threshold voltage roll-off according to structural parameters of sub-10 nm asymmetric double gate MOSFET. In case of sub-10nm channel length, because of short channel effects resulting from the rapid increase of tunneling current, even asymmetric double gate (DG) MOSFET, which has been developed for reducing short channel effects, will increase threshold voltage roll-off, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Especially, since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top/bottom oxide thickness will affect the threshold voltage roll-off. To analyze this, thermal emission current and tunneling current model have been calculated, and threshold voltage roll-off in accordance with the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off, in particular, is generated more greatly according to silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage

The Impact of Tunneling on the Subthreshold Swing in Sub-20 nm Asymmetric Double Gate MOSFETs

<p>This paper analyzes the subthreshold swing in asymmetric double gate MOSFETs with sub-20 nm channel lengths. The analysis of the carrier transport in the subthreshold region of these nano scaled MOSFET includes tunneling as an important additional mechanism to the thermionic emission. It is found that the subthreshold swing is increasing due to tunneling current and that the performance of nano scaled MOSFETs is degraded. The degradation of the subthreshold swing due to tunneling is quantified using analytical potential distribution and Wentzel–Kramers–Brillouin (WKB) approximation in this paper. This analytical approach is verified by two dimensional simulation. It is shown that the degradation of subthreshold swing increases with both reduction of channel length and increase of channel thickness. We also show that the subthreshold swing is increasing in case of different top and bottom gate oxide thicknesses.</p>

Optimum top and bottom oxide thicknesses and flat-band voltages for improving subthreshold characteristics of 5 nm DGMOSFET

This paper has proposed the optimum design rules as investigating subthreshold characteristics of 5 nm DG (Double Gate) MOSFET for top/bottom gate flat-band voltages and oxide thicknesses. The difference of top gate voltages between on-current (10−7A) and off-current (10−12A) is specified as ΔVon−off, and the top-gate voltage for the on-current is defined as the threshold voltage. ΔVon−off and the threshold voltage are derived from equations for the drain current and gate voltage for various top/bottom gate flat-band voltages and oxide thicknesses, and compared with those for symmetric structure having equal top/bottom gate flat-band voltages and oxide thicknesses. As a result, the potential distributions for top/bottom gate flat-band voltages and oxide thicknesses influence on directly the tunneling current, which greatly changes ΔVon−off and the threshold voltage in subthreshold region. It is established that the top flat-band voltage and oxide thickness have to be larger than the bottom flat-band voltage and oxide thickness to reduce ΔVon−off and threshold voltage, compared with those of symmetric structure.

비대칭 DGMOSFET의 상하단 산화막 두께비에 따른 터널링 전류 분석

ABSTRACT This paper analyzes the deviation of tunneling current for the ratio of top and bottom gate oxide thickness of short channel asymmetric double gate(DG) MOSFET. The ratio of tunneling current for off current significantly increases if channel length reduces to 5 nm. This short channel effect occurs for asymmetric DGMOSFET having different top and bottom gate oxide structure. The ratio of tunneling current in off current with parameters of channel length and thickness, doping concentration, and top/bottom gate voltages is calculated in this study, and the influence of tunneling current to occur in short channel is investigated. The analytical potential distribution is obtained using Poisson equation and tunneling current using WKB(Wentzel-Kramers-Brillouin). As a result, tunneling current is greatly changed for the ratio of top and bottom gate oxide thickness in short channel asymmetric DGMOSFET, specially according to channel length, channel thickness, doping concentration, and top/bottom gate voltages.

비대칭 이중게이트 MOSFET에서 상단과 하단 산화막 두께비가 문턱전압이하 스윙에 미치는 영향

ABSTRACT Asymmetric double gate(DG) MOSFET has the different top and bottom gate oxides thicknesses. It is analyzed the deviation of subthreshold swing(SS) and conduction path for the ratio of top and bottom gate oxide thickness of asymmetric DGMOSFET. SS varied along with conduction path, and conduction path varied with top and bottom gate oxide thickness. The asymmetric DGMOSFET became valuable device to reduce the short channel effects like degradation of SS. SSs were obtained from analytical potential distribution by Poisson’s equation, and it was analyzed how the ratio of top and bottom oxide thickness influenced on conduction path and SS. SSs and conduction path were greatly influenced by the ratio of top and bottom gate oxide thickness. Bottom gate voltage cause significant influence on SS, and SS are changed with a range of 200 mV/dec for      under bottom voltage of 0.7 V. 키워드 : 비대칭 이중게이트, 문턱전압이하 스윙, 전도중심, 상하단 산화막 두께비 Key word : Asymmetric Double Gate, Subthreshold Swing, Conduction Path, Ratio of Top and Bottom Gate Oxide Thickness

High-directionality fiber-chip grating coupler with interleaved trenches and subwavelength index-matching structure.

We present the first experimental demonstration of a new fiber-chip grating coupler concept that exploits the blazing effect by interleaving the standard full (220 nm) and shallow etch (70 nm) trenches in a 220 nm thick silicon layer. The high directionality is obtained by controlling the separation between the deep and shallow trenches to achieve constructive interference in the upward direction and destructive interference toward the silicon substrate. Utilizing this concept, the grating directionality can be maximized independent of the bottom oxide thickness. The coupler also includes a subwavelength-engineered index-matching region, designed to reduce the reflectivity at the interface between the injection waveguide and the grating. We report a measured fiber-chip coupling efficiency of -1.3 dB, the highest coupling efficiency achieved to date for a surface grating coupler in a 220 nm silicon-on-insulator platform fabricated in a conventional dual-etch process without high-index overlays or bottom mirrors.

Quantum Mechanical Electrostatics and Transport Simulation and Performance Evaluation of Short Channel Monolayer WSe2 Field Effect Transistor

In this work a numerical electrostatics and transport simulator is developed for monolayer WSe2 channel Field Effect Transistor considering Quantum Mechanical effects. The electrostatics simulator solves 1-D Schrödinger-Poisson equation self-consistently in the direction perpendicular to the channel. Whereas, the transport simulator employs Fast Uncoupled Mode Space (FUMS) approach with Non-Equlibrium Green’s Function (NEGF) formalism. The simulator explored 20 nm long monolayer WSe2 channel FET with top and bottom oxide thickness 3 and 5 nm respectively. This device showed excellent ON state performance with maximum ON current reaching up to 467.2 A/m and maximum transconductance of 887.7 S/m. On the other hand, the OFF state and short channel performances also showed promise with 1010 on/off current ratio, 77.72 mV/dec Subthreshold Slope (SS) and 14.91 mV/V Drain Induced Barrier Lowering (DIBL). The overall performance reveals great potential of this monolayer WSe2 FET in many low power and high speed applications.

비대칭 이중게이트 MOSFET의 차단전류에 대한 전도중심 의존성 분석

Asymmetric double gate(DG) MOSFET is a novel transistor to be able to reduce the short channel effects. This paper has analyzed a off current for conduction path of asymmetric DGMOSFET. The conduction path is a average distance from top gate the movement of carrier in channel happens, and a factor to change for oxide thickness of asymmetric DGMOSFET to be able to fabricate differently top and bottom gate oxide thickness, and influenced on off current for top gate voltage. As the conduction path is obtained and off current is calculated for top gate voltage, it is analyzed how conduction path influences on off current with parameters of oxide thickness and channel length. The analytical potential distribution of series form is derived from Poisson’s equation to obtain off current. As a result, off current is greatly changed for conduction path, and we know threshold voltage and subthreshold swing are changed for this reasons

10 nm이하 비대칭 이중게이트 MOSFET의 하단 게이트 전압에 따른 터널링 전류 분석

This paper analyzed the deviation of tunneling current for bottom gate voltage of sub-10 nm asymmetric double gate MOSFET. The asymmetric double gate MOSFET among multi gate MOSFET developed to reduce the short channel effects has the advantage to increase the facts to be able to control the channel current, compared with symmetric double gate MOSFET. The increase of off current is, however, inescapable if aymmetric double gate MOSFET has the channel length of sub-10 nm. The influence of tunneling current was investigated in this study as the portion of tunneling current for off current was calculated. The tunneling current was obtained by the WKB(Wentzel-Kramers-Brillouin) approximation and analytical potential distribution derived from Poisson equation. As a results, the tunneling current was greatly influenced by bottom gate voltage in sub-10 nm asymmetric double gate MOSFET. Especially it showed the great deviation for channel length, top and bottom gate oxide thickness, and channel thickness.

이중게이트 MOSFET의 대칭 및 비대칭 산화막 구조에 대한 문턱전압 분석

본 연구에서는 대칭 및 비대칭 산화막 구조를 가진 이중게이트(double gate; DG) MOSFET의 문턱전압 변화에 대하여 분석하였다. 상하단 동일한 산화막 두께을 갖는 대칭 DGMOSFET와 달리 비대칭 DGMOSFET는 상하단 게이트 산화막 두께를 다르게 제작할 수 있다. 그러므로 비대칭 DGMOSFET에서 상단과 하단게이트 산화막 두께의 크기 변화에 따라 대칭 DGMOSFET와 문턱전압을 비교하여 상하단 게이트 산화막 두께의 최적값에 대하여 고찰하고자 한다. 문턱전압을 구하기 위하여 포아송방정식에서 해석학적 전위분포모델을 유도하였으며 도핑분포함수는 가우스분포함수를 사용하였다. 문턱전압 모델을 이용하여 하단게이트 전압, 채널길이 및 채널두께 등에 따라 상하단게이트 산화막 두께가 문턱전압에 미치는 영향을 관찰하였다. 결과적으로 문턱전압은 상하단 게이트 산화막 두께에 따라 크게 변화하였으며 변화하는 경향은 하단게이트 전압, 채널길이 그리고 채널두께에 따라 매우 상이하게 나타나고 있다는 것을 알 수 있었다. This paper has analyzed the change of threshold voltage for oxide structure of symmetric and asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET can be fabricated with different top and bottom gate oxide thickness, while the symmetric DGMOSFET has the same top and bottom gate oxide thickness. Therefore optimum threshold voltage is considered for top and bottom gate oxide thickness of asymmetric DGMOSFET, compared with the threshold voltage of symmetric DGMOSFET. To obtain the threshold voltage, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. We investigate for bottom gate voltage, channel length and thickness, and doping concentration how top and bottom gate oxide thickness influences on threshold voltage using this threshold voltage model. As a result, threshold voltage is greatly changed for oxide thickness, and we know the changing trend greatly differs with bottom gate voltage, channel length and thickness, and doping concentration.

비대칭 이중게이트 MOSFET의 상하단 산화막 두께비에 따른 전도중심에 대한 문턱전압 의존성

ABSTRACT This paper has analyzed the change of threshold voltage and conduction path for the ratio of top and bottom gate oxide thickness of asymmetric double gate MOSFET. The asymmetric double gate MOSFET has the advantage that the factor to be able to control the current in the subthreshold region increases. The analytical potential distribution is derived from Poisson’s equation to analyze the threshold voltage and conduction path for the ratio of top and bottom gate oxide thickness. The Gaussian distribution function is used as charge distribution. This analytical potential distribution is used to derive off-current and subthreshold swing. By observing the results of threshold voltage and conduction path with parameters of bottom gate voltage, channel length and thickness, projected range and standard projected deviation, the threshold voltage greatly changed for the ratio of top and bottom gate oxide thickness. The threshold voltage changed for the ratio of channel length and thickness, not the absolute values of those, and it increased when conduction path moved toward top gate. The threshold voltage and conduction path changed more greatly for projected range than standard projected deviation.

Fiber-chip grating coupler based on interleaved trenches with directionality exceeding 95.

We propose a fiber-chip grating coupler that interleaves the standard full and shallow etch trenches in a 220 nm thick silicon layer to provide a directionality upward exceeding 95%. By adjusting the separation between the two sets of trenches, constructive interference is achieved in the upward direction independent of the bottom oxide thickness and without any bottom reflectors, overlays, or customized etch depths. We implement a transverse subwavelength structure in the first two grating periods to minimize back-reflections. The grating coupler has a calculated coupling efficiency of CE~-1.05 dB with a 1 dB bandwidth of 30 nm and minimum feature size of 100 nm, compatible with deep-UV lithography.

비대칭 DGMOSFET의 문턱전압이하 스윙에 대한 게이트 산화막 의존성 분석

비대칭 이중게이트(double gate; DG) MOSFET의 문턱전압이하 스윙의 게이트 산화막 두께에 대한 변화를 고찰하였으며 이를 위하여 포아송방정식의 해석학적 전위분포를 구하였다. 특히 포아송방정식을 풀 때 도핑분포함수에 가우시안 함수를 적용함으로써 보다 실험값에 가깝게 해석하였다. 비대칭 DGMOSFET 소자는 대칭적 구조를 갖는 DGMOSFET와 달리 4단자 소자로서 상단과 하단의 게이트 산화막 두께 및 인가전압을 달리 설정할 수 있다. 비대칭 DGMOSFET의 문턱전압이하 스윙을 상 하단 게이트 산화막 두께 변화에 따라 관찰한 결과, 게이트 산화막 두께에 따라 문턱전압이하 스윙은 크게 변화하는 것을 알 수 있었다. 특히 상 하단 게이트 산화막 두께가 증가할 때 문턱전압이하 스윙 값도 증가하였으며 상단 게이트 산화막 두께의 변화가 문턱전압이하 스윙 값에 더욱 큰 영향을 미치고 있다는 것을 알 수 있었다. This paper has presented the change of subthreshold swings for gate oxide thickness of asymmetric double gate(DG) MOSFET, and solved Poisson equation to obtain the analytical solution of potential distribution. The Gaussian function as doping distribution is used to approch experimental results. The symmetric DGMOSFET is three terminal device. Meanwhile the asymmetric DGMOSFET is four terminal device and can separately determine the bias voltage and oxide thickness for top and bottom gates. As a result to observe the subthreshold swings for the change of top and bottom gate oxide thickness, we know the subthreshold swings are greatly changed for gate oxide thickness. Especially we know the subthreshold swings are increasing with the increase of top and bottom gate oxide thickness, and top gate oxide thickness greatly influences subthreshold swings.

Improvement of Bottom Oxide Thickness Scaling of Inter-Poly Dielectric by Floating Gate Top Plasma Nitridation

This letter concerns the electrical properties of floating gate (FG) that has undergone top nitridation, used in NAND flash memory devices As the dimensions are scaled down to 5 nm and beyond, the use of a thinner inter-poly dielectric (IPD) can provide the required gate coupling ratio, leaving more room for the control gate poly filling between the FG. However, the effect of the IPD scaling on data retention capability is the main bottleneck. Two interesting retention failure phenomena are demonstrated in a sample of thin bottom poly oxide (BPO). They are attributed to the enhanced degradation of the electrical field at the top corners of the FG and the potential difference between neighboring FG along the WL direction. These phenomena must be taken into consideration while setting the limits of the BPO in the IPD film scheme. The proposed FG top nitridation overcomes this limitation on the thinning of the bottom oxide improving the data retention characteristics of NAND flash memory devices.

Polarization-independent grating coupler for micrometric silicon rib waveguides

Grating couplers are a promising approach to implement efficient fiber-chip coupling. However, their strong polarization dependence makes dual-polarization operation challenging. In this Letter we propose, for the first time, a polarization-independent grating coupler for thick rib silicon-on-insulator (SOI) waveguides. Coupling efficiency is optimized by designing the grating pitch and duty cycle, without varying the bottom oxide thickness, which significantly simplifies practical implementation. Directivity of the grating coupler is enhanced by a high reflectivity layer under the bottom oxide after the selective removal of the Si substrate. Dual-polarization coupling efficiency of -2.8 dB is shown.

Modeling the Impact of the Trench Depth on the Gate–Drain Capacitance in Power MOSFETs

Trench depth is important in low-voltage trench MOSFETs because it affects the switching losses through the gate-drain capacitance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> ). The dependence of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> on the trench depth is investigated by analytical modeling and experimental characterization. An analytical model that relates the trench depth, trench bottom oxide thickness, n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> layer doping, and drain voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VD</i> ) to <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> is developed and validated by experimental measurements. Trench MOSFETs with thick bottom oxides have been fabricated with 1.3-, 1.5-, 1.7-, and 2-μm deep trenches. <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CV</i> measurements show that <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> is proportional to the trench depth at low <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VD</i> and becomes increasingly independent of trench depth as <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VD</i> is increased. The model is used to show that this is due to <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> being dominated by the oxide capacitance at low <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VD</i> and the depletion capacitance at high <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VD</i> . The fact that the average thickness of the trench bottom oxide decreases as the trench depth increases (because of additional sidewall oxide overlapping the drain) means that the impact of the trench depth is the highest at low <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VD</i> , where the depletion capacitance is ineffective.