Thermo-mechanical Reliability Issues Research Articles

(Invited) Understanding the Pre-Failure Thermo-Mechanical Issues in Electromigration of TSV Enabled 3D ICs

Traditional metrology has been unable to adequately address the needs of emerging integrated circuits at the nano scale; thus, new metrology and techniques are needed. For example, the reliability challenges, and their root causes, in TSV enabled 3D-IC fabrication need to be well understood and controlled to enable mass production. This requires new approaches to the metrology. In this paper, we use microwave propagation characteristics (S-parameters) to study the thermo-mechanical reliability issues that precede electromigration failures in Cu-filled TSVs. The pre-failure insertion losses and group delay are reversibly dependent on both the device temperature and the amount of current forced through the devices under test. This is attributed to the plasticity of the copper fill in the TSVs.

(Invited) Understanding the Pre-Failure Thermo-Mechanical Issues in Electromigration of TSV Enabled 3D ICs

Traditional metrology has been unable to adequately address the needs of emerging integrated circuits at the nano scale; thus, new metrology and techniques are needed. For example, the reliability challenges, and their root causes, in TSV enabled 3D-IC fabrication need to be well understood and controlled to enable mass production. This requires new approaches to the metrology. In this paper, we use microwave propagation characteristics (S-parameters) to study the thermo-mechanical reliability issues that precede electromigration failures in Cu-filled TSVs. The pre-failure insertion losses and group delay are reversibly dependent on both the device temperature and the amount of current forced through the devices under test. This is attributed to the plasticity of the copper fill in the TSVs.

Engineering Thermal Conductivity for Balancing Between Reliability and Performance of Bulk Thermoelectric Generators

The nanostructuring approach has significantly contributed to the improving of thermoelectric figure‐of‐merit (ZT) by reducing lattice thermal conductivity. Even though it is an effective method to enhance ZT, the drastically lowered thermal conductivity in some cases can cause thermomechanical issues leading to decreased reliability of thermoelectric generators. Here, an engineering thermal conductivity (κeng) is defined as a minimum allowable thermal conductivity of a thermoelectric material in a module, and is evaluated to avoid thermomechanical failure and thermoelectric degradation of a device. Additionally, there is dilemma of determining thermoelectric leg length: a shorter leg is desired for higher W kg−1, W cm−3, and W $−1, but it raises the thermomechanical vulnerability issue. By considering a balance between the thermoelectric performance and thermomechanical reliability issues, it is discussed how to improve device reliability of thermoelectric generators and the engineering thermal conductivity of thermoelectric materials.

Survey of High-Temperature Reliability of Power Electronics Packaging Components

In order to take the full advantage of the high-temperature SiC and GaN operating devices, package materials able to withstand high-temperature storage and large thermal cycles have been investigated. The temperature under consideration here are higher than 200 °C. Such temperatures are required for several potential applications such as down-hole oil and gas industry for well logging, aircrafts, automotive, and space exploration. This review focuses on the reliability of a selection of potential components or materials used in the package assembly as the substrates, the die attaches, the interconnections, and the encapsulation materials. It reveals that, substrates with low coefficient of thermal expansion (CTE) conductors or with higher fracture resistant ceramics are potential candidates for high temperatures. Die attaches and interconnections reliable solutions are also available with the use of compatible metallization schemes. At this level, the reliability can also be improved by reducing the CTE mismatch between assembled materials. The encapsulation remains the most limiting packaging component since hard materials present thermomechanical reliability issues, while soft materials have low degradation temperatures. The review allows identifying reliable components and materials for high-temperature wide bandgap semiconductors and is expected to be very useful for researchers working for the development on high-temperature electronics.

Runtime Self-Calibrated Temperature–Stress Cosensor for 3-D Integrated Circuits

On-chip temperature and stress sensors are important for runtime system management techniques tackling thermomechanical reliability issues in 3-D integrated circuits (ICs). However, traditional temperature and stress sensor designs require large calibration overhead to improve accuracy, which incurs significant cost for massive production. To address the challenge, in this paper, we propose a novel temperature–stress cosensor design for 3-D ICs. By exploring the inherent reciprocity of temperature and stress mechanisms, it achieves runtime self-calibration such that no dedicated calibration effort is needed. Simulation results show that the cosensor achieves 0.26 $^{\circ}{\rm C}$ and 0.43 MPa accuracy on average in temperature and stress measurements, respectively, when evaluated in $[{-}60^{\circ}{\rm C}, 140^{\circ}{\rm C}]$ . In addition, the accuracy of self-calibrated sensors remains within 1.1 $^{\circ}{\rm C}$ and 2.3 MPa when there exists up to 5% measurement noise, which shows that the self-calibration process is relatively insensitive to various noises.

Reliability investigations for high temperature interconnects

Purpose – Because of the need for electronics use at temperatures beyond 150°C, high temperature resistant interconnection technologies like transient liquid phase (TLP) soldering and silver sintering are being developed which are not only replacements of high-lead solders, but also open new opportunities in terms of temperature resistance and reliability. The paper aims to address the thermo-mechanical reliability issues that have to be considered if the new interconnection technologies will be applied. Design/methodology/approach – A TLP soldering technique is briefly introduced and new challenges concerning the thermo-mechanical reliability of power devices are worked out by numerical analysis (finite element simulation). They arise as the material properties of the interconnect materials differ substantially from those known for soft solders. The effective material responses of the new materials are determined by localized unit cell models that capture the inhomogeneous structure of the materials. Findings – It is shown that both the TLP solder layer and the Ag-sinter layer have much less ductility and show less creep than conventional soft solders. The potential failure modes of an assembly made by TLP soldering or Ag sintering change. In particular, the characteristic low cycle fatigue solder failures become unlikely and are replaced either by metallization fatigue, brittle failure of intermetallic compound, components, or interfaces. Originality/value – A variety of new failure risks, which have been analyzed theoretically, can be avoided only if they are known to the potential user of the new techniques. It is shown that an optimal reliability will be strongly dependent on the actual assembly design.

수치해석에 의한 TSV 구조의 열응력 및 구리 Protrusion 연구

Through-Silicon Via (TSV) 기술은 3차원 적층 패키징를 위한 핵심 기술로서 큰 관심을 받고 있다. 그러나 TSV 기술은 아직 다양한 공정상의 문제와 신뢰성 문제를 해결해야 하는 난제가 남아 있다. 특히 구리 비아(via)와 실리콘 기판의 큰 열팽창계수의 차이로 인한 열응력은 계면 박리, 크랙 발생, 구리 protrusion 등 다양한 신뢰성 문제를 발생시킨다. 본 연구에서는 구리 TSV 구조의 열응력을 수치해석을 이용하여 분석하였으며, 3차원 TSV 비아와 실리콘 기판의 응력 및 변형을 해석하였다. 비아의 크기, 비아와 비아 사이의 간격 및 비아의 밀도가 TSV 구조의 응력에 미치는 영향을 분석하였으며, 또한 어닐링(annealing) 온도 및 비아의 크기가 구리 protrusion에 미치는 영향을 관찰하였다. 구리 TSV 구조의 신뢰성을 향상시키기 위해서는 적절한 비아와 비아 사이의 간격을 유지한 상태에서, 비아의 크기 및 비아의 밀도는 작아야 한다. 또한 구리 protrusion을 감소시키기 위해서는 비아의 크기 및 어닐링 공정과 같은 공정의 온도를 낮추어야 한다. 본 연구의 결과는 TSV 구조의 열응력과 관련된 신뢰성 이슈를 이해하고, TSV 구조의 설계 가이드라인을 제공하는데 도움을 줄 수 있을 것으로 판단된다. The through-silicon via (TSV) technology is essential for 3-dimensional integrated packaging. TSV technology, however, is still facing several reliability issues including interfacial delamination, crack generation and Cu protrusion. These reliability issues are attributed to themo-mechanical stress mainly caused by a large CTE mismatch between Cu via and surrounding Si. In this study, the thermo-mechanical reliability of copper TSV technology is investigated using numerical analysis. Finite element analysis (FEA) was conducted to analyze three dimensional distribution of the thermal stress and strain near the TSV and the silicon wafer. Several parametric studies were conducted, including the effect of via diameter, via-to-via spacing, and via density on TSV stress. In addition, effects of annealing temperature and via size on Cu protrusion were analyzed. To improve the reliability of the Cu TSV, small diameter via and less via density with proper via-to-via spacing were desirable. To reduce Cu protrusion, smaller via and lower fabrication temperature were recommended. These simulation results will help to understand the thermo-mechanical reliability issues, and provide the design guideline of TSV structure.

Efficient damage sensitivity analysis of advanced Cu/low- k bond pad structures by means of the area release energy criterion

For integrated circuit (IC) wafer back-end development, state-of-the-art CMOS-technologies have to be developed and robust bond pad structures have to be designed in order to guarantee both functionality and reliability during waferfab processes, packaging, qualification tests, and, of course, usage. It is now well established that for future CMOS-technologies (CMOS065 and beyond), low- k dielectric materials will be integrated in the back-end structures. However, bad thermal and mechanical integrity as well as weak interfacial adhesion result in major thermo-mechanical reliability issues. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily induce cracking, delamination and chipping of the IC back-end structure when no appropriate precautions are taken. This paper presents an efficient method to describe the damage sensitivity of three-dimensional multi-layered structures. The index that characterizes this failure sensitivity is an energy measure called the Area Release Energy, which predicts the amount of energy that is released upon crack initiation at an arbitrary position along an interface. The benefits of the method are: (1) the criterion can be used as damage sensitivity indicator for complex three-dimensional structures; (2) the criterion is energy-based, thus more accurate than stress-based criteria; (3) unlike recent fracture mechanics approaches, no initial defect size and location has to be assumed a priori. A mesh objectivity condition is formulated resulting from numerical experiments. The method is applied to advanced IC back-end structures, revealing not only the most critical back-end design but also the critical interfaces in the bond pad structures at which delamination might occur. In order to bridge the length scale difference between the wafer level and the back-end structures, a multi-scale method has been implemented in the finite element code MSC.Marc. In this way, effects of e.g., packaging and wire bond loading at the global level can be studied while taking into account the possibility of occurring failure phenomena at the local, back-end level. The validity and applicability of the method will be demonstrated by considering several Cu/low- k back-end structures. The obtained results are in good agreement with experimental observations.

Discussion on the Reliability Issues of Solder-Bump and Direct-Solder Bonded Power Device Packages Having Double-Sided Cooling Capability

Power device packages with solder-bump (SB) and direct-solder (DS) interconnections were fabricated and some of their thermomechanical reliability issues were discussed based on both thermal cycling experiment and finite element analysis (FEA). The SB interconnection shows superior reliability over the DS interconnection in the thermal cycling experiment because the mismatched coefficient of thermal expansion leads to smaller stresses at the SB interconnection under the same temperature changes. On the other hand, FEA results show that the DS package has significantly lower operating temperatures under the same double-sided cooling condition. After considering the operating temperature difference, the DS package was shown to be superior over the SB package in the power cycling analysis.

Thermomechanical reliability of underfilled BGA packages

The effect of underfill on various thermomechanical reliability issues in super ball grid array (SBGA) packages is studied in this paper. Nonlinear finite element models with underfill and no underfill are developed taking into consideration the process-induced residual stresses. In this study, the solder is modeled as time and temperature-dependent, while other materials are modeled temperature and direction-dependent, as appropriate. The stress/strain variations in the package due to thermal cycling are analyzed. The effect of underfill is studied with respect to magnitude and location of time-independent plastic strain, time-dependent creep strain and total inelastic strain in solder balls. The effect of copper core on the solder ball strains is presented. The possibility of delamination at the interposer-underfill interface as well as substrate-underfill interface is studied with the help of qualitative interfacial stress analysis. Results on SBGA packages indicate that the underfill does not always enhance BGA reliability, and that the properties of the underfill have a significant role in the overall reliability of the BGA packages. The predicted number of thermal cycles to solder joint fatigue are compared with the existing experimental data on similar nonunderfilled BGA packages.