Thermal-aware Scheduling Algorithms Research Articles

Server temperature prediction using deep neural networks to assist thermal-aware scheduling

Thermal-Aware (TA) scheduling is a primitive thermal-management tool to avoid hotspots and attain a better thermal profile inside data centers. However, TA scheduling depends on the accuracy of server temperature calculation for making reliable scheduling decisions. Existing TA simulation frameworks rely on the CRAC, RC, and thermodynamics model to calculate the temperature of a server. However, these models are not very efficient computationally while calculating the temperature of computing nodes. Hence, there is a need for an efficient and lightweight temperature prediction model to fill this gap. Moreover, existing TA allocation and migration schemes neglect the workload heterogeneity regarding execution time (length) of user tasks in batch workloads. Ignoring task heterogeneity may lead to higher ambient temperature on its neighboring servers—assigning a hotter job with a longer duration to a server with higher ambient effect results in significantly higher cooling expenses.Our contribution in this paper is twofold: (1) firstly, we design and train a deep neural network to predict the temperature of servers; our proposed DNN model achieves 96.11% prediction accuracy, and (2) secondly, we propose a TA algorithm for job allocation and migration. Specifically, we consider the length and thermal profile of user tasks and servers during allocation and migration. We compare the proposed strategy against existing TA scheduling designs such as TA Scheduling Algorithm (TASA) and TA Control Strategy (TACS) using simulations. Results demonstrate that the proposed TA approach significantly reduces the overall energy consumption by up to 12.03% and 8.28% compared to the TASA and TACS, respectively.

Thermal-aware resource allocation in earliest deadline first using fluid scheduling

Thermal issues in microprocessors have become a major design constraint because of their adverse effects on the reliability, performance and cost of the system. This article proposes an improvement in earliest deadline first, a uni-processor scheduling algorithm, without compromising its optimality in order to reduce the thermal peaks and variations. This is done by introducing a factor of fairness to earliest deadline first algorithm, which introduces idle intervals during execution and allows uniform distribution of workload over the time. The technique notably lowers the number of context switches when compare with the previous thermal-aware scheduling algorithm based on the same amount of fairness. Although, the algorithm is proposed for uni-processor environment, it is also applicable to partitioned scheduling in multi-processor environment, which primarily converts the multi-processor scheduling problem to a set of uni-processor scheduling problem and thereafter uses a uni-processor scheduling technique for scheduling. The simulation results show that the proposed approach reduces up to 5% of the temperature peaks and variations in a uni-processor environment while reduces up to 7% and 6% of the temperature spatial gradient and the average temperature in multi-processor environment, respectively.

Enhancing Energy Efficiency in Temperature Controlled Dynamic Scheduling Technique for Multi Processing System on Chip

Microprocessors design consist of many micro level chips that reaches to a state where thermal upsurge occurs due to rapid processing of data and effect (reduce) their efficiency in many different aspects. That production of heat can cause disintegration which makes the chips disable of doing many function they are assign to perform. Embedded devices are designed to combine hardware and software, software integration can insert to hardware to perform some specific function. Multicore embedded devices are in different shapes and dimension. It has various applications on larger scale in networking and nuclear powerhouses to small multimedia players printers, automobiles, cameras mobile handset due to higher demand of power the energy becomes the major concern of the multicore devices for this a thermal aware scheduling algorithm has been proposed that consider the migration of load from higher state to that of lower state and considers all type of tasks and forecast them according to the priority by maintaining the previous history. The proposed technique also considers various thermal values by consulting the previous priorities of task on multicore systems. Migration policy is used to share load from one core to another the algorithm efficiently decreases almost 3℃ temperatures at 40% utilization and the energy utilization is 221.3 J which is 3.12 % improved as compare to the global EDF

Temperature Minimization and Thermal-Driven Scheduling for Real-Time Periodic Tasks

With the increasing power density of processors due to the continuous shrinking of chip size, thermal issue of real-time systems has become more and more urgent since it can greatly affect the systems’ reliability and safety. However, due to the difficulty in quantitative analysis of temperature, existing thermal-aware research either considers temperature as a constraint to minimize energy consumption treating leakage power as a constant, or minimizes the temperature qualitatively through approaches like cool-hot task execution pattern. Even the latest work also only analyzes the average temperature in thermal steady state. To this end, this paper aims at quantitatively minimizing the temperature in both steady and transient states while considering the effect of temperature on leakage power. The following contributions have been made: presents a method of task construction, based on which the minimal temperature condition for any scheduling algorithm like GPS (Global Processor Sharing) and EDF (Earliest Deadline First) under both steady and transient states is proved; discovers a thermal law exhibited by tasks’ power consumption, based on which a thermal-aware approximate algorithm of GPS with a relatively longer scheduling length is designed to mitigate the higher switching overhead of GPS scheduling while guaranteeing the tasks’ timing constraints. Sufficient experiments validate the minimal temperature condition and thermal-aware scheduling algorithm. The two important conclusions obtained from this work are: (1) when the optimal condition can be achieved, all of the scheduling algorithms like GPS and EDF result in the same minimal temperature traces since all of the tasks share the same power consumption value and the processor is fully utilized; (2) when not, the executing sequence of tasks in a scheduling interval of the approximate GPS scheduling, which is determined based on the thermal law, exhibits a better thermal-aware feature.

Decentralized Thermal-Aware Task Scheduling for Large-Scale Many-Core Systems

Technology scaling has enabled fast increase in the number of cores integrated in many-core systems. However, feature size shrinking also makes large-scale many-core systems vulnerable to thermal failures. Thermal-aware task scheduling is an efficient technique to reduce the run-time temperatures of many-core processors. Most existing thermal-aware task scheduling algorithms leverage centralized scheduling schemes to gather the overall information and generate the task schedule at a center scheduler. Although that scheme can achieve the optimal temperature reduction, however, it faces severe computation bottleneck and communication congestion when the many-core processors evolve to large-scale with hundreds or thousands of cores. In this paper, we propose a decentralized thermal-aware scheduling algorithm to address this problem in large-scale systems. Experiment results on various benchmarks show that our decentralized algorithm achieves significant improvement on scalability (up to 84.3% reduction in monitoring traffic) and similar benefits on temperature reduction (by 5%) when compared with the state-of-the-art thermal-aware scheduling algorithm.

Thermal-Aware Task Scheduling for 3D-Network-on-Chip: A Bottom to Top Scheme

Three-dimensional network-on-chip (3D-NoC) emerges as a potential multi-core architecture delivering high performance, high energy efficiency and great scalability. However, 3D-NoC suffers from severe thermal problems due to its high power density. To solve this problem, thermal-aware scheduling is an effective solution. However, the high complexity of the thermal model of 3D-NoC becomes a major hurdle for developing efficient thermal-aware scheduling algorithms for 3D-NoC. In this paper, we propose a novel thermal-aware task scheduling scheme named as the Bottom-to-Top (B2T) approach to address this challenge. This heuristic-based method performs task allocation on processing units to efficiently minimize the peak temperature and improve the execution time of the tasks with low complexity. The algorithm is first designed for two-layer 3D-NoC and then extended to 3D-NoC with an arbitrary number of layers. When compared to traditional thermal-aware scheduling algorithms designed for 2D-NoC, our B2T algorithm can achieve significant peak temperature reduction (up to 11.9[Formula: see text]C) and performance improvement (up to 4%) on two-layer 3D-NoC. The improvement becomes more significant as the number of layers in 3D-NoC increases. For four-layer 3D-NoC, the improvement is up to [Formula: see text]C peak temperature reduction.

An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs

For any given application, there is an optimal throughput point in the space of per-processor performance and the number of such processors given to that application. However, due to thermal, yield, and other constraints, not all of these optimal points can plausibly be constructed with a given technology. In this paper, we look at how emerging steep slope devices, 3D circuit integration, and trends in process technology scaling will combine to shift the boundaries of both attainable performance, and the optimal set of technologies to employ to achieve it. We propose a heterogeneous-technology 3D architecture capable of operating efficiently at an expanded number of points in this larger design space and devise a heterogeneity and thermal aware scheduling algorithm to exploit its potential. Our heterogeneous mapping techniques are capable of producing speedups ranging from 17% for a high end server workloads running at around 90°C to over 160% for embedded systems running below 60°C