Testing Mixed-signal Circuits Research Articles

Design an Identification Function to Reduce the Computational Resources on the Testing Process of an Analog Electronic Circuit

In modern electronic circuits, imperfectness in the technological process can cause errors in reaching the correct values of the functional parameters. In order to solve this problem, a novel approach of analog and mixed-signal circuit testing methodology is used. The presented approach allows the testing complexity to be reduced and the testing time to be decreased. For this paper, selected signal features were designated from the transient output signal response. Using regression models with the extracted signal features, the functional parameters of a circuit were determined. An evolutionary determination of the regression models enabled the efficiency of the identification process to be maximized. The proposed methodology is presented for an exemplary CMOS Dickson charge pump circuit.

Adaptive Test With Test Escape Estimation for Mixed-Signal ICs

The standard approach in industry for post-manufacturing testing of mixed-signal circuits is to measure the performances that are included in the data sheet. Despite being accurate and straightforward, this approach involves a high test time since there are numerous performances that need to be measured sequentially by switching the circuit into different test configurations. Adaptive test is a new test paradigm that still adheres to the standard approach, but it adjusts it on-the-fly to the particularities of the circuit under test so as to better control test time and to achieve robust outlier detection. In this paper, we present an adaptive test flow for mixed-signal circuits that has comprehensive user-defined parameters to span the tradeoff between test time savings and fault coverage so as to select an advantageous point on the curve based on test economics. The flow also provides robust test escape risk estimation so as to add confidence to the test process. The proposed idea is demonstrated on a sizable production dataset from a large mixed-signal circuit.

Multi-Directional Space Tessellation to Improve the Decision Boundary in Indirect Mixed-Signal Testing

One of the most challenging aspects in nowadays microelectronics industry is production test and verification of mixed-signal circuits. In order to cope with some of the drawbacks encountered in this scenario, researchers have found alternate test as a promising solution in achieving such endeavor. This work prospects the possibilities of using space tessellations along multiple directions in order to improve the test decision boundary definition in the alternate measure space. The proposed method is able to reduce false positive test outcomes, i.e. test escapes, with acceptable penalty in test yield loss metric. The key idea presented in this work is to use an ensemble of octrees, each of them tessellating the plane along different directions. Such tessellations create a refinement in the non linear test decision boundaries without the need of including extra circuit samples. The tree ensemble, together with a strict test decision criterion, serve as a classifier during the production testing phase. The proposed multi-directional ensemble tessellation strategy has been applied to test a band-pass Biquad filter affected by parametric variations. The proposed method has reported promising simulation results in lowering the test escapes metric as compared to a single octree classifier. The computational overhead of evaluating several octrees is insignificant since 2n-tree data structures are traversed efficiently. The octree ensemble technique has also been compared against a classic specification guard-banding technique reporting better test yield loss metrics for the same test escape target.

Speeding Up Analog Integration and Test for Mixed-Signal SoCs [From the EIC

Presents an editorial that addresses the main topics discussed in this issue focusing on the complex challenges of design, verification, and test of analog and mixed-signal circuits and SoCs.

Designing nonlinearity characterization for mixed-signal circuits in system-on-chip

Long test times and the use of conventional automatic test equipment (ATE) makes conventional mixed-signal linearity performance testing costly. Diminishing test time of linearity test significantly reduces system-on-a-chip production test costs and, therefore, lessens total product manufacturing costs. Several low-cost linearity test methods have addressed this issue for a single-ended mixed-signal circuit testing. On the other hand, a low-cost test approach has rarely been proposed for differential mixed-signal circuits, due to a new class of test obstacles from differential circuits that are widely employed for high-speed I/O products. This paper presents a cost-effective self-test methodology to characterize the linearity performance of differential mixed-signal circuits in loopback mode. The proposed method precisely predicts the device-under-test (DUT) linearity specifications by building accurate DUT nonlinear polynomial models using spectral specifications from recent work. The test cost is significantly reduced by replacing conventional ATE with the proposed self-test platform and by reducing test time to a fraction of conventional testing time. Hardware measurement results validated the test performance of the proposed test scheme.

Efficient and Accurate Testing of On-Chip ADC Based on ATE

The embedded digital-analog mixed-signal circuit testing has become one of the difficulties to be solved. In this paper, a SoC embedded ADC has been tested based on the Credence Gemini500 verification system. The testing method is studied and verified through the test experiment and results. This testing method is an important reference for general embedded IP core testing.

Pseudorandom Test of Nonlinear Analog and Mixed-Signal Circuits Based on a Volterra Series Model

This paper presents new test methods for nonlinear Analog and Mixed-Signal (AMS) circuits which use a pseudorandom signal to test multiple Devices Under Test (DUTs) accurately. The goal of the studies presented in this paper is to understand the behaviors of nonlinear AMS circuits in a low-cost test environment and to develop the algorithm to extract the performance information of the DUTs using simple test measurements. The extracted information is then used to estimate the various specifications of DUTs. In order to achieve this goal, we analyze the behaviors of AMS circuits using a Volterra series model, and investigate the stochastic properties of the pseudorandom signals to develop the efficient performance characterization algorithms. The mathematical theory and experimental results are presented to validate the presented test methods.

An ADC BIST with on-chip ramp generator

This work presents built-in self-test (BIST) techniques for the production testing of mixed signal circuits. The special test strategy for the typical mixed-signal component analog-to-digital converter (ADC) is discussed. The traditional test for such mixed-signal components can be completed through a DSP-based mixed-signal tester with an arbitrary waveform generator and a signal digitizer, but such a test is very costly and time consuming. Hence, a BIST strategy based on an on chip ramp generator (OCRG) is proposed in this work for testing ADC. This BIST method has an advantage testing ADC without DAC to overcome area overhead. This BIST method realizes the test controller, test pattern generation and output response analyser at the aspect of the on-chip circuitry. The demonstration of the proposed BIST is given through various simulation results in the last parts of this work.

A novel DFT technique for testing complete sets of ADCs and DACs in complex SiPs

Testing mixed-signal circuits remains one of the most difficult challenges within the semiconductor industry. In this article, the authors present a novel DFT technique to test sets of ADCs and DACs embedded in a complex SiP. The technique provides fully digital testing on the converters to significantly reduce the cost of testing

A low-cost digital frequency testing approach for mixed-signal devices using ΣΔ modulation

This paper presents a digital approach to frequency testing of Analogue and mixed-signal (AMS) circuits. This approach is aimed at facilitating low-cost test techniques for system-on-chip (SoC) devices, rendering the test of mixed-signal cores compatible with the use of a low-cost digital tester. Analogue test signal generation is performed on-chip by low pass filtering a sigma–delta (ΣΔ) encoded bit-stream. Analogue harmonic test response analysis is also performed on-chip using square wave modulation and ΣΔ modulation. Since both analogue signal generation and test response analysis are digitally programmable on-chip, compatibility with a low-cost digital tester is ensured. Optimisation of test signatures is discussed in detail as a trade-off between fault and yield coverage. A 0.18μm CMOS implementation of this BIST technique is presented, including some experimental results.

Testing Biquad Filters under Parametric Shifts Using X-Y Zoning

Testing mixed-signal circuits is a difficult task due to defect modeling challenges, observability and controllability restrictions and ATE bandwidth limitations. In this paper, the X-Y Zoning test of a Biquad filter is addressed to select the optimal excitation frequency and the best partition of the X-Y plane. Thus we obtain the best sensitivity of the BIST scheme to parametric shifts of the parameters defining the filter. The study has been particularized to shifts in the natural frequency f0 of the Biquad filter. Analytical results on the best input as well as the best partition of the observed X-Y Lissajous plots are obtained. Extensive MATLAB simulations validate the proposal, which has also been validated experimentally. For these experiments, multiple implementations of the Biquad with nominal and shifted parameters have been performed using a commercial Field Programmable Analog Array (FPAA). The experimental measures show good correlation with the analytical expressions and the simulations performed, and validate the proposed testing methodology.

A built-in current sensor using thin-film transistors

A simple current mirror using TFTs with input terminals which are capacitively coupled to the TFT gate, is used in this work, to design a built-in current sensor (BICS). The important feature in this application is that the voltage drop across the sensing TFT device can be reduced to almost zero value, while preserving transistor operation in the saturation region. This makes the proposed BICS appropriate for TFT applications without affecting the circuit operation. It also results in adequate linearity for the current monitoring, making the structure applicable to digital as well as to analog and mixed-signal circuit testing.

Subband Filtering for Time and Frequency Analysis of Mixed-Signal Circuit Testing

A new technique is proposed to analyze and compress the output responses from analog circuits. We first describe the subband filtering scheme to decompose responses from the analog circuit under test (CUT). A subband or wavelet filter takes the response, then generates the decomposed signals for each frequency band. The decomposed signal for each frequency band is rectified and then fed into its respective integrator. Two kinds of wavelet filters are used to decompose the test response and effectively detect the faults in the circuit. Implementation issues including hardware overhead are also discussed.

BIST and production testing of ADCs using imprecise stimulus

A new approach for testing mixed-signal circuits based upon using imprecise stimuli is introduced. Unlike most existing Built-In Self-Test (BIST) and production test approaches that require excitation signals that are at least 3 bits or more linear than the Device-Under-Test (DUT), the proposed approach can work with stimuli that are several bits less linear than the DUT. This dramatically reduces the requirements on stimulus generation for BIST applications and offers potential for using inexpensive signal generators in production test, or for testing DUTs that have a linearity performance exceeding that of the available test equipment. As a proof of concept, a histogram-based algorithm for linearity testing for Analog-to-Digital Converters (ADCs) has been proposed. It can estimate the Integral Nonlinearity (INL) and Differential Nonlinearity (DNL) of an n -bit ADC by using a ramp signal of much less than n -bit linearity and a shifted version of the same nonlinear ramp as excitation. The performance of the algorithm is comparable to that of the traditional method which uses ( n + 3)-bits or a decade more linear input signals. Complete algorithm description, extensive simulation results and experimental results obtained from using a production tester on commercially available ICs are presented to validate the potential of this algorithm.

Modeling a verification test system for mixed-signal circuits

In contrast to the large number of logic gates and storage circuits encountered in digital networks, purely analog networks usually have relatively few circuit primitives (operational amplifiers and so on). The complexity lies not in the number of building blocks but in the complexity of each block and the need to test a range of parameters-for example, gain, bandwidth, and signal-to-noise ratio. Degraded circuit performance as well as nonfunctional operation must be checked. Thus, circuit complexity rather than volume complexity is the dominant problem in analog test, and testing mixed-signal circuits entails more difficulties than testing purely digital circuits. In IC manufacturing, circuits traditionally move from design to test with little thought about how each department's activities affect those of the other. This lack of foresight almost always results in iteration cycles between design and test to realize a testable design that also satisfies the specification. We need a bridge between design and test phases to enable a smooth transition. An integrated approach whereby both teams understand each other's requirements is a big step in the right direction; interaction between design and test databases significantly increases the degree to which design and test development can operate as concurrent processes; some work has already been done in this area. Our goal was to build Spice models for the instruments incorporated in the IntegraTest system so that we could simulate the tests this system conducts during design. The models are based on manufacturer specifications, and control parameters used in the models are as close as possible to those in the instruments. To make changes in the models transparent to users, entering of parameters is isolated from the models' internal construction. After building the models, we compared the results of the simulated tests with results from actual tests performed with real instruments.

Integrated Design and Test of Mixed-Signal Circuits

In this paper, the integration of design and test flows for mixed-signal circuits is discussed. The aim is to decrease test generation and debugging costs and time-to-market for the analogue blocks in mixed-signal circuits. A tool developed in order to automate the data sharing between design and test environments is described and the functionality of this tool is explained. The generation of a test plan consists of the selection of the separate test functions and addition of commands for control signal generation and tester routing. The usage of design data for each of these functions is explained and the tool is evaluated in the design and testing of a mixed-signal demonstrator circuit. Results from this experience are discussed.

Testing of analogue and mixed-signal circuits by using supply current measurements

A complete (hardware and software) system has been designed and implemented, which can measure the supply current (IPS) of analogue and mixed-mode circuits and detect or diagnose faults, based on RMS and spectrum calculations of the IPS and the corresponding fault dictionary. The system is applied to testing and diagnosis of various analogue and mixed-signal circuits, showing very encouraging results.

A tutorial introduction to research on analog and mixed-signal circuit testing

Traditionally, work on analog testing has focused on diagnosing faults in board designs. Recently, with increasing levels of integration, not just diagnosing faults, but distinguishing between faulty and good circuits has become a problem. Analog blocks embedded in digital systems may not easily be separately testable. Consequently, many papers have been recently written proposing techniques to reduce the burden of testing analog and mined-signal circuits. This survey attempts to outline some of this recent work, ranging from tools for simulation-based test set development and optimization to built-in self-test (BIST) circuitry.

Application of Dynamic Supply Current Monitoring to Testing Mixed-Signal Circuits

This paper applies the time-domain testing technique and compares the effectiveness of transient voltage and dynamic power supply current measurements in detecting faults in CMOS mixed-signal circuits. The voltage and supply current (iDDT) measurements are analyzed by three methods to detect the presence of a fault, and to establish which measurement achieves higher confidence in the detection. Catastrophic, soft and stuck-at single fault conditions were introduced to the circuit-under-test (CUT). The time-domain technique tests a mixed-signal CUT in a unified fashion, thereby eliminating the need to partition the CUT into separate analogue and digital modules.

Mixed current/voltage observation towards effective testing of analog and mixed-signal circuits

Power supply current monitoring is a promising technique for the development of new test methodologies for analog and mixed-signal circuits. The advantages of efficiency and reduced test time have already been recognized in the digital domain. This paper shows that improved test efficiency and detection confidence are obtained when both output voltage and power supply current are observed. Results found from the simulation of two circuits are presented comparing fault detection ratios and the amplitude of faulty response deviations when observing each one of these signals. Cross-correlation between output voltage and power supply current is presented as a means to perform a single mixed current/voltage testing operation, providing at the same time increased efficiency. It allows also for simplifications on test circuitry and processing, as reductions on the sampling rates and amplitude resolutions used to acquire the signals provide the same fault coverage levels obtained using higher fidelity measurements.