Test Generation For Combinational Circuits Research Articles

Hierarchical test generation for combinational circuits with real defects coverage

This paper deals with the automatic test pattern generation (ATPG) technique at the higher level using a functional fault model and defect-fault relationship in the form of a defect coverage table at the lower level. The paper contributes to test pattern generation (TPG) techniques taking into account physical defect localisation. A new parameter––probabilistic effectiveness of input patterns––has been used in the TPG technique with the goal of increasing real defect coverage. This parameter is based on probabilities of physical defects in digital cells which may occur in real integrated circuits. This improvement has been implemented into the existing DefGen ATPG system for combinational circuits.

Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization

Motivated by the problem of test pattern generation in digital circuits, this paper presents a novel technique called recursive learning that is able to perform a logic analysis on digital circuits. By recursively calling certain learning functions, it is possible to extract all logic dependencies between signals in a circuit and to perform precise implications for a given set of value assignments. This is of fundamental importance because it represents a new solution to the Boolean satisfiability problem. Thus, what we present is a new and uniform conceptual framework for a wide range of CAD problems including, but not limited to, test pattern generation, design verification, as well as logic optimization problems. Previous test generators for combinational and sequential circuits use a decision tree to systematically explore the search space when trying to generate a test vector. Recursive learning represents an attractive alternative. Using recursive learning with sufficient depth of recursion during the test generation process guarantees that implications are performed precisely; i.e., all necessary assignments for fault detection are identified at every stage of the algorithm so that no backtracks can occur. Consequently, no decision tree is needed to guarantee the completeness of the test generation algorithm. Recursive learning is not restricted to a particular logic alphabet and can be combined with most test generators for combinational and sequential circuits. Experimental results that demonstrate the efficiency of recursive learning are compared with the conventional branch-and-bound technique for test generation in combinational circuits. In particular, redundancy identification by recursive learning is demonstrated to be much more efficient than by previously reported techniques. In an important recent development, recursive learning has been shown to provide significant progress in design verification problems. Also importantly, recursive learning-based techniques have already been shown to be useful for logic optimization. Specifically, techniques based on recursive learning have already yielded better optimized circuits than the well known MIS-II.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Dynamic redundancy identification in automatic test generation

Test generation for combinational circuits, an NP-complete problem, shows its worst-case behavior while trying to generate tests for redundant faults and failing after an exhaustive search. The performance of an automatic test generator can be significantly improved by identifying redundancy via simple techniques which do not involve a search. The authors present a technique to identify redundant faults. This technique works dynamically during test generation, but is not based on a search process. It relies on test-covering relations among faults, which allow identification of addition redundant faults after the test generator fails to generate a test for a target fault. This technique has been implemented in AT&T's Testpilot test generation system and has shown a reduction of up to 32% in the number of backtracks in test generation runs. >

Automatic test pattern generation on parallel processors

Test generation for combinational circuits is an important step in the VLSI design process. Unfortunately, the problem is highly computation-intensive and for circuits encountered in practice, test generation time can often be enormous. In this paper, we present a parallel formulation of the backtrack search algorithm called PODEM, which is a highly used algorithm for this problem. It is known that the sequential PODEM algorithm consumes most of its execution time in generating tests for ‘hard-to-detect’ (HTD) faults and is often unable to detect them even after a large number of backtracks. Our parallel formulation overcomes these limitations by dividing the search space and searching it concurrently using multiple processes. We present a number of experimental results and show that these match our theoretical results presented elsewhere. We show that the search efficiency of the parallel algorithm improves and even beats that of the sequential algorithm as the ‘hardness’ of a fault increases. We present speedup results and performance analyses of our formulation on a 128 processor Symult s2010 multicomputer. We also present preliminary results on a network of Sun workstations. Our results show that parallel search techniques provides good speedups as well as high fault coverage of the HTD faults in reasonable time when compared to the uniprocessor implementation. Our experimental validation of most of our theoretical results builds confidence in the following theoretical prediction: our parallel formulation of PODEM is highly scalable on a variety of commercially-available, large MIMD parallel processors (in additions to the ones with which we experimented).

A complete critical path algorithm for test generation of combinational circuits

It is known that critical path test generation method is not a complete algorithm for combinational circuits with reconvergent-fanout. In order to make it a complete algorithm, we put forward a reconvergent-fanout-oriented technique, the principal critical path algorithm, propagating the critical value back to primary inputs along a single path, the principal critical path, and allowing multiple path sensitization if needed. Relationship among test patterns is also discussed to accelerate test generation.

Fault simulation and test generation in combinational circuits using atomic digraphs

Atomic digraphs are applied to fault description and simulation in combinational circuits. Using these graphs, it is possible to simulate both the correct circuit and the presence of any simple or multiple stuck-at fault. The proposed method permits the efficient generation of tests.