Terms Of Energy-delay Product Research Articles

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

This paper proposes a novel architecture of excess-1 adder-based Carry Select Adder (M2CSA) using single leaf cell i.e., 2–1 Multiplexer. M2CSA is designed using a new type of Excess-1 block. The Excess-1 block is designed in a distinct way using 2–1 multiplexers. The architectures of the proposed carry select adder and its internal excess-1 blocks are completely distinct when compared to existing carry select adders. The proposed 4-, 8-, 16-, 32-, and 64-bit M2CSAs use a 2–1 multiplexer only. The complex gates such as XOR gates are eliminated which exist in existing Carry Select Adders (CaSeAs). A 64-bit M2CSA that utilises one kind of 2-1 Mux cell is clearly decomposed to retain outstanding cell regularity. In previous designs, ripple carry adder blocks are substituted with half adders by limiting carry propagation to a particular degree. By avoiding carry propagation over adder blocks, particularly in 32- and 64-bit adders, the performance of M2CSA is initially increased. For CaSeAs, the area is of primary significance; for M2CSAs, it is also diminished by preserving cell regularity. Verilog HDL is utilised in the design of the M2CSA and current CaSeAs. Using Cadence NCLaunch, all of the designs are functionally tested. At a 90nm technology node, all of the designs are generated and executed using Genus and Innovus tools, respectively. As a comparison to prior designs, the 64-bit M2CSA final ASIC architecture is on average 17% less in terms of space. The comparison and result analysis show that 64-bit M2CSA performs 20% and 19% faster than 64-bit SQCSC in terms of performance and power dissipation, respectively.. The proposed 4-, 8-, 16-, 32-, 64- bit M2CSA exhibits less PDP (Power-Delay Product) ranging from 25%–30% concerning SQCSCs. Similarly, EDP (Energy- Delay Product) values for all the designs are calculated. The improvement in EDP for the 4-, 8-, 16-, 32-, 64- bit M2CSA is 41, 38, 42, 43, and 45 percentages compared to 4-, 8-, 16-, 32-, 64- bit SQCSC respectively. Therefore, the M2CSAs outperform the existing designs in terms of EDP by 38%–45%.

Reducing DRAM refresh power consumption by runtime profiling of retention time and dual-row activation

Refresh power of dynamic random-access memory (DRAM) has become a critical problem due to the large memory capacity of servers and mobile devices. It is imperative to reduce refresh rate in order to reduce refresh power consumption. However, current methods of refresh rate improvement have limitations such as large area/performance overhead, low system availability, and lack of support at the memory controller. We propose a novel scheme which comprises three essential functions: (1) an adaptive refresh method that adjusts refresh period on each DRAM chip, (2) a runtime method of retention-time profiling that operates inside DRAM chips during idle time thereby improving availability, and (3) a dual-row activation method which improves weak cell retention time at a very small area cost. The proposed scheme allows each DRAM chip to refresh with its own refresh period without requiring the external support. Experiments based on real DRAM chip measurements show that the proposed methods can increase refresh period by 4.5 times at 58 °C by adjusting refresh period in a temperature-aware manner while incurring only a small overhead of 1.05% and 0.02% in DRAM chip area and power consumption, respectively. Below 58 °C, our method improves the refresh period by 12.5% compared with two state-of-the-art methods, AVATAR and in-DRAM ECC. In various memory configurations with SPEC benchmarks, our method outperforms the existing ones in terms of energy-delay product by 19.7% compared with the baseline, and by 15.4% and 12.4%, with respect to AVATAR and in-DRAM ECC, respectively.

Intrinsic Performance of Germanane Schottky Barrier Field-Effect Transistors

Germanane (GeH), a hydrogenated germanium monolayer, is a new family of 2-D semiconductors, exhibiting promising potential for electronic device applications. Here, we investigate GeH Schottky barrier (SB) field-effect transistors (FETs) using atomistic quantum transport simulations. Our simulation results reveal that the ohmic-contact device with zero SB height ( $\Phi _{\text {Bn}}$ ) exhibits ~20% lower ON-current than the metal-oxide-semiconductor (MOS) FET counterpart due to the inherent tunnel barrier at the metal–semiconductor junction. We also compare 14-nm-channel GeH and black phosphorus (BP) SBFETs with a finite SB height of $\Phi _{\text {Bn}} = 0.22$ eV for both devices. Our results show that GeH outperforms BP in the ON-state, but it can suffer from larger leakage current in the OFF-state. We further investigate the effect of barrier height in GeH SBFET by varying $\Phi _{\text {Bn}}$ from 0 eV to a half bandgap (0.78 eV). In general, as barrier height increases, both ON-current and the minimum leakage current are reduced. It is also observed that, with increasing SB height, intrinsic delay increases but the required energy per switching decreases, indicating the trade-off between the device speed and the energy dissipation. Our benchmarking of GeH SBFET against GeH and BP MOSFETs demonstrates that GeH generally outperforms BP in terms of energy-delay product (EDP). By performing careful engineering of SB height along with the device threshold voltage, we show that the minimum EDP of GeH SBFET can be as comparable as that of the MOSFET counterpart, suggesting great potential of GeH SBFETs for future switching device applications.

Double-precision Dual Mode Logic carry-save multiplier

In this paper, a double-precision carry-save adder (CSA)-based array multiplier is designed using the Dual Mode Logic (DML) approach in a commercial 65-nm low-power CMOS technology. DML typically allows on-the-fly controllable switching at the gate level between static and dynamic operation modes. The proposed multiplier exploits this unique ability of DML to efficiently trade performance and energy consumption when considering on-demand double-precision (8 × 8-bit or 16 × 16-bit) operations. This occurs in the DML multiplier working in a mixed operation mode, i.e., by employing the static and dynamic mode for lower and higher precision operations, respectively. In fact, the use of the dynamic mode for higher precision operations ensures higher performance as compared to the standard CMOS circuit (16% gain on average) at the cost of higher energy consumption. Such energy penalty is counterbalanced at lower precision operations where the static mode is enabled in the DML circuit. Overall, the adoption of the mixed operation mode in the proposed DML multiplier proves to be beneficial to achieve a better performance/energy trade-off with respect to the standard CMOS implementation and to the case when using either the static or the dynamic mode for both operations at the two different precisions. When compared to its CMOS counterpart, our DML design operating in the mixed mode exhibits an average improvement of 15% in terms of energy-delay product (EDP) under wide-range supply voltage scaling. Such benefit is maintained over process-voltage-temperature (PVT) variations.

Dynamic Frequency Scaling Regarding Memory for Energy Efficiency of Embedded Systems

Memory significantly affects the power consumption of embedded systems as well as performance. CPU frequency scaling for power management could fail in optimizing the energy efficiency without considering the memory access. In this paper, we analyze the power consumption and energy efficiency of an embedded system that supports dynamic scaling of frequency for both CPU and memory access. The power consumption of the CPU and the memory is modeled to show that the memory access rate affects the energy efficiency and the CPU frequency selection. Based on the power model, a method for frequency selection is presented to optimize the power efficiency which is measured using Energy-Delay Product (EDP). The proposed method is implemented and tested on a commercial smartphone to achieve about 3.3% - 7.6% enhancement comparing with the power management policy provided by the manufacturer in terms of EDP.

Assessment of Germanane Field-Effect Transistors for CMOS Technology

Using self-consistent atomistic quantum transport simulations, the device characteristics of n-type and p-type germanane (GeH) field-effect transistors (FETs) are evaluated. While both devices exhibit near-identical off-state characteristics, n-type GeH FET shows ~40% larger on current than the p-type counterpart, resulting in faster switching speed and lower power-delay product. Our benchmark of GeH FETs against similar devices based on 2D materials reveals that GeH outperforms MoS2 and black phosphorus in terms of energy-delay product (EDP). In addition, the performance of GeH-based CMOS circuit is analyzed using an inverter chain. By engineering power supply voltage and threshold voltage simultaneously, we find the optimal operating condition of GeH FETs, minimizing EDP in the CMOS circuit. Our comprehensive study, including material parameterization, device simulation, and circuit analyses, demonstrates significant potential of GeH FETs for 2D-material CMOS circuit applications.

Performance Benchmarking of 32 nm Predictive Technology Model CMOS with Silicon Nanowire Physic-Based Compact Model of Field-Effect Transistors for Digital Logic Applications

New variation of nanostructures are introduced and developed to sustain Moore's Law as device dimension is scaled drastically. Among those low dimensional technological innovation is silicon (Si) nanowire field-effect transistor (NWFET). The usefulness of Si NWFET is its compatibility with existing complementary metal-oxide semiconductor (CMOS) technology that been widely pursued for more than four decades. Device simulation of nanowire is essential to explore physics in depth and to assess, quantify and benchmark the device performance metrics with a nanoscale metal-oxide semiconductor field-effect transistor (MOSFET). SPICE model of Si NWFET is constructed based on the device model proposed by researchers from Purdue University. A semi-empirical solution of the self-consistent is presented so that the device model is made portable and can be simulated in SPICE and other platform. Then, silicon-based digital logic circuit namely inverter, NOR and NAND are simulated and analysed. The circuit performances of nanowire digital gates are then compared against 32 nm MOSFET in terms of energy-delay product, power-delay product, propagation delay and average power dissipation. The results shown that silicon nanowires perform better than 32 nm MOSFET generally due to the high velocity transport of quasi ballistic carriers and superior gate control.

Power-aware code scheduling assisted with power gating and DVS

Traditionally, code scheduling is used to optimize the performance of an application, because it can rearrange the code to allow the execution of independent instructions in parallel based on instruction level parallelism (ILP). According to our observations, it can also be applied to reduce power dissipation by taking advantage of the properties of existing low-power techniques. In this paper, we present a power-aware code scheduling (PACS), which is a code scheduling integrated with power gating (PG) and dynamic voltage scaling (DVS) to reduce power consumption while executing an application. In other words, from the viewpoint of compilation optimization, PG and DVS can be applied simultaneously to a code and their impact can be enhanced by code scheduling to further save power. The result shows that when compared with hardware power gating, the proposed PACS can outperform by more than 33% and 41% in terms of energy delay product and energy delay2 product for DSPStone and Mediabench.

Selecting representative benchmark inputs for exploring microprocessor design spaces

The design process of a microprocessor requires representative workloads to steer the search process toward an optimum design point for the target application domain. However, considering a broad set of workloads to cover the large space of potential workloads is infeasible given how time-consuming design space exploration typically is. Hence, it is crucial to select a small yet representative set of workloads, which leads to a shorter design cycle while yielding a (near) optimal design. Prior work has mostly looked into selecting representative benchmarks; however, limited attention was given to the selection of benchmark inputs and how this affects workload representativeness during design space exploration. Using a set of 1,000 inputs for a number of embedded benchmarks and a design space with around 1,700 design points, we find that selecting a single or three random input(s) per benchmark potentially (in a worst-case scenario) leads to a suboptimal design that is 56% and 33% off, on average, relative to the optimal design in our design space in terms of Energy-Delay Product (EDP). We then propose and evaluate a number of methods for selecting representative inputs and show that we can find the optimum design point with as few as three inputs.

Performance and Energy Impact of Locally Controlled NML Circuits

This article quantitatively considers the performance of nanomagnetic logic circuits within the context of realistic drive circuitry. We also demonstrate how one of the five fundamental tenets of digital logic---preventing unwanted feedback---can be satisfied by realistic drive circuitry. More specifically, different types of multiphase clocks are investigated and compared. Initial projections suggest that even with drive circuitry overhead, nanomagnet logic can outperform subthreshold CMOS in terms of energy delay product---and paths to lower power exist.

Rotary router

The trend towards increasing the number of processor cores and cache capacity in future Chip-Multiprocessors (CMPs), will require scalable packet-switched interconnection networks adapted to the restrictions imposed by the CMP environment. This paper presents an innovative router design, which successfully addresses CMP cost/performance constraints. The router structure is based on two independent rings, which force packets to circulate either clockwise or anti-clockwise, traveling through every port of the router. It uses a completely decentralized scheduling scheme, which allows the design to: (1) take advantage of wide links, (2) reduce Head of Line blocking, (3) use adaptive routing, (4) be topology agnostic, (5) scale with network degree, and (6) have reasonable power consumption and implementation cost. A thorough comparative performance analysis against competitive conventional routers shows an advantage for our proposal of up to 50 % in terms of raw performance and nearly 60 % in terms of energy-delay product.