Device Temperature Research Articles

Research on Junction Temperature Smooth Control of SiC MOSFET Based on Body Diode Conduction Loss Adjustment

In a converter of actual working condition, the change in the current and voltage of the power device will cause the junction temperature to fluctuate greatly. This device is subjected to high thermal stress due to the change in the junction temperature. Therefore, it is necessary to adopt junction temperature control to reduce or smooth the junction temperature fluctuation, so as to realize the junction temperature control and improve the reliability of the device. At present, the methods for the junction temperature control of power devices have certain limitations and there are few active thermal management methods proposed for SiC device characteristics. In this paper, a method for realizing the smooth control of the junction temperature of a SiC device based on the conduction loss adjustment of the body diode for the SiC device has been proposed, considering that the conduction loss of the body diode is greater than the conduction loss of the SiC MOSFET. The conduction time of SiC MOSFET body diode was adjusted. By adjusting the conduction loss of the SiC MOSFET device, the fluctuation range of the junction temperature of the SiC MOSFET device was controlled, the smooth control of the junction temperature of the SiC device was realized, and the thermal stress of the device was reduced.

Fully printed zero-static power MoS2 switch coded reconfigurable graphene metasurface for RF/microwave electromagnetic wave manipulation and control

Reduction of power consumption is the key target for modern electronic devices. To this end, a lot of attention is paid to zero-static power switches, being able to change their state between highly resistive and highly conductive and remain in this state even in the absence of external voltage. Still, the implementation of such switches is slow because of compatibility issues of new materials with CMOS technology. At the same time, printable technology enables low-cost processes at ambient temperature and integration of devices onto flexible substrates. Here we demonstrate that printed Ag/MoS2/Ag heterostructures can be used as zero-static power switches in radiofrequency/microwave spectrum and fully-integrated reconfigurable metasurfaces. Combined with graphene, our printed platform enables reconfigurable metasurface for electromagnetic wave manipulation and control for wireless communications, sensing, and holography. In addition, it is also demonstrated that the localised MoS2 phase change may have promoted Ag diffusion in forming conductive filaments.

Thermal boundary conductance enhancement of the Si/diamond interface via atomic transition strategy

Developing multi-chip systems introduces significant thermal management challenges, due to dense vertical stacking and interconnections. Specifically, the increased number of interfaces within the heat conduction path of the chips significantly impedes the effective heat transfer. This study utilizes a series of molecular dynamics simulations to explore how the structure and atomic composition at interfaces affect their thermal conduction abilities. This study initially reveals substantial differences in thermal conduction capabilities between Si/Diamond, SiC/Diamond, and Diamond/Diamond interfaces. Further investigations focus on interfaces between different structures of SiC and diamond, clearly identifying the atomic composition and structure at the interface as key factors influencing thermal boundary conductance (TBC). Based on these findings, the study proposes a strategy for atomic transition that involves inserting SiC into the Si/Diamond interface. Under optimal thickness conditions for the SiC transition layer, a significant increase in theoretical TBC is achieved, from 477.1 MW/m²K to 701.1 MW/m²K, which is twice the value predicted by the existing diffusive mismatch model (DMM) for Si/Diamond interfaces. Lastly, through the developed 3D IC model, the study examines the impact of TBC variations on the peak temperature of the entire device, thereby further emphasizing the importance of enhancing interface thermal conduction capabilities. This series provides strategic guidance for thermal management in 3D ICs and offers a theoretical basis for chip design and material selection.

Increasing coil temperature of a third-generation e-cigarette device modulates C57BL/6 mouse lung immune cell composition and cytokine milieu independently of aerosol dose

ABSTRACT Higher coil temperature in e-cigarette devices increases the formation of aerosols and toxicants, such as carbonyls. At present, the health implications of vaping at higher temperatures, including exacerbation of pulmonary inflammation, are largely unknown when aerosol dose is considered. To isolate the pulmonary effects of coil temperature, C57BL/6 mice were exposed to e-cigarette aerosols generated at lower (190°C) or higher (250°C) temperature for 3 days, while maintaining a similar chamber aerosol concentration. Increasing coil temperature did not markedly alter aerosol mass-normalized emissions of select carbonyls formed from thermal degradation pathways including formaldehyde, acetaldehyde, propionaldehyde, and acetone under the tested environment. Total bronchoalveolar cells, primarily macrophages, were significantly decreased in mice exposed to aerosols generated with higher coil temperatures compared to lower temperature exposures. The gene expression of IFNβ, IL-1β, TNFα, and IL-10 in mouse lung tissue was significantly reduced following e-cigarette exposure under both conditions, compared to filtered air exposure. Higher temperature exposures further exacerbated downregulation of IFNβ and IL-1β. Data suggest that higher temperature vaping might modulate acute pulmonary immune responses, potentially inducing immune suppression, even when normalized for aerosol dose exposure. Coil temperature thus appears to be an important parameter that needs to be regulated to ensure harm reduction for e-cigarette users.

Probing the limits for coherent optical control of a mechanically decoupled defect center in hexagonal boron nitride

The coherent control of a two-level system is among the most essential challenges in modern quantum optics. Understanding its fundamental limitations is crucial, also for the realization of next generation quantum devices. The quantum coherence of a two-level system is fragile in particular, when the two levels are connected via an optical transition, which, at the same time, enables the manipulation of the system. When such quantum emitters are located in solids the coherence suffers from the interaction of the optical transition with the solid state environment, which requires the sample to be cooled to temperatures of a few Kelvin or below. Here, we use a mechanically isolated quantum emitter in hexagonal boron nitride to explore the individual mechanisms which affect the coherence of an optical transition under resonant drive. We operate the system at the threshold where the mechanical isolation collapses in order to study the onset and temperature-dependence of dephasing and independently of spectral diffusion. The insights on the underlying physical decoherence mechanisms reveal a limit in temperature until which coherent driving of the system is possible. This study enables to increase the operation temperature of hBN-based quantum devices, therefore reducing the need for cryogenic cooling.

Enhancing the Thermal Stability of Skyrmion in Magnetic Nanowires for Nanoscale Data Storage.

Magnetic skyrmion random switching and structural stability are critical limitations for storage data applications. Enhancing skyrmions' magnetic properties could improve their thermal structural stability. Hence, micromagnetic calculation was carried out to explore the thermal nucleation and stability of skyrmions in magnetic nanodevices. Different magnetic properties such as uniaxial magnetic anisotropy energy (Ku), saturation magnetization (Ms) and Dzyaloshinskii-Moriya interaction (DMI) were used to assess the thermal stability of skyrmions in magnetic nanowires. For some values of Ms and Ku, the results verified that the skyrmion structure is stable at temperatures above 800 K, which is higher than room temperature. Additionally, manipulating the nanowire geometry was found to have a substantial effect on the thermal structural stability of the skyrmion in storage nanodevices. Increasing the nanowire dimensions, such as length or width, enhanced skyrmions' structural stability against temperature fluctuations in nanodevices. Furthermore, the random nucleation of the skyrmions due to the device temperature was examined. It was shown that random skyrmion nucleation occurs at temperature values greater than 700 K. These findings make skyrmion devices suitable for storage applications.

Experimental investigation of an additively manufactured cold plate for multi-chip module cooling generated using the homogenization approach to topology optimization

The homogenization approach to topology optimization is promising for generating high-performance, liquid-cooled cold plates due to its ability to create sub-resolution features by optimizing the spatial distribution and porosities of physical microstructures. This optimization capability has been demonstrated for the design of compact microchannel heat sinks under uniform heating conditions. However, there is a need to understand its applicability for practical applications involving complex boundary conditions posed by modern electronics packaging requirements. This work performs the topology optimization, design for manufacturing, fabrication, and experimental testing of a liquid-cooled cold plate for an application-representative multi-chip module with eight devices. The cold plate design requirements and boundary conditions involve eight equally spaced heat generating sources and liquid inlet/outlet ports that are off-center, introducing flow distribution challenges to the thermal design. A topology optimization algorithm is developed using the homogenization approach with circular pin fins chosen as the microstructure. An empirical permeability correlation for pin fins is developed which is implemented in the porous media flow model of the topology optimization algorithm to simulate pressure drop across additively manufactured pin fins. In addition to the topology optimized designs, a benchmark cold plate design with uniformly distributed 1.2 mm diameter pin fins, representative of the feature dimensions currently adopted in applications for the investigated boundary conditions, is also evaluated. Comparison of the topology optimized cold plate generated using the design freedom brought by additive manufacturing to the benchmark design highlights the optimizer’s ability to uniformly distribute the coolant amongst the heated regions. The maximum base temperature rise is 35.5 °C for the benchmark design versus 6.6 °C for the topology optimized design. Flow uniformity combined with the high convective heat transfer of the sub-resolution fins and channels in the vicinity of the heated regions keep the device temperatures low. The topology optimized cold plate is additively manufactured and experimentally tested at various flow rates. The experimental results match well with the model predictions, with a mean absolute percentage error of 5.5 % and 9.7 % for pressure drop and thermal resistance respectively, indicating that the optimal performance promised by the algorithm can be realized using additively manufactured parts. The work presented here demonstrates the overall process flow for the homogenization approach in leveraging the capabilities of additive manufacturing to generate high-performance liquid cold plates for practical applications.

Phase change thermal interface film with bicontinuous and textured filler network for efficient wearable heat dissipation

Wearable thermal management needs to simultaneously meet thermal conductivity, heat storage capacity, stability, flexibility, and economy, but these characteristics constrain each other in the development of phase change thermal interface materials (PhC-TIM). Therefore, relying on the economic bicontinuous structure for fillers’ orientation, a new type of bicontinuous phase change thermal interface material (BPTIM) was designed, which includes thermal storage phase composed of paraffin (PCMs) and flexible molecule styrene–butadiene–styrene (SBS), and thermal conductivity phase composed of adhesive polyurethane (PU) and thermal conductive medium hexagonal boron nitride (h-BN). In the experiment, shear force generated by stirring and optimized two-phase volume ratio resulted in the stretching and compressing of the thermal conductive phase, promoting the orientation of h-BN and forming a textured thermal-conductive network in a high PCMs content bicontinuous structure. Moreover, the introduction of SBS had brought bending resistance and thermal stability. These characteristics enabled BPTIMs to significantly reduce the surface temperature of the wearable device by 23 °C. Overall, this design provides a certain reference for the widespread application of PhC-TIM in thermal management of wearable electronic products.

Understanding Process-Structure Relationships during Lamination of Halide Perovskite Interfaces.

Fabrication of halide perovskite (HP) solar cells typically involves the sequential deposition of multiple layers to create a device stack, which is limited by the thermal and chemical incompatibility of top contact layers with the underlying HP semiconductor. One emerging strategy to overcome these restrictions on material selection and processing conditions is lamination, where two half-stacks are independently processed and then diffusion bonded to complete the device. Lamination reduces the processing constraints on the top side of the solar cell to allow new device designs, expanded use of deposition methods, and self-encapsulation of devices. While laminated perovskite solar cells with high efficiencies and novel interlayer combinations have been demonstrated, there is a limited understanding of how the lamination process parameters affect the diffusion-bond quality and material properties of the resulting HP layer. In this study, we systematically vary temperature, pressure, and time during lamination and quantify the resulting impacts on bonded area, grain domain size, and photoluminescence. A design of experiments is performed, and statistical analysis of the experimental results is used to quantitatively evaluate the resulting process-structure-property relationships. The lamination temperature is found to be the key parameter controlling these properties. A temperature of 150 °C enables successful bonding over 95% of the substrate area and also results in increases in apparent grain domain size and photoluminescence intensity. Based on these insights, the lamination temperature of functional perovskite solar cell devices is varied, demonstrating the importance of the resulting bond quality on device performance metrics.

Hardware Testing Methodologies for Wide Bandgap High-Power Converters

Wide bandgap (WBG) power semiconductor devices are increasingly replacing silicon IGBTs in high-power and high-voltage power electronics applications. However, there is a significant gap in the literature regarding efficient testing methodologies for high-power and high-voltage converters under constrained laboratory resources. This paper addresses this gap by presenting comprehensive, hardware-focused testing methodologies for high-power and high-voltage WBG power semiconductor-based converter bring-up before the control validation phase steps in. The proposed methods enable thorough evaluation and validation of converter hardware, including device switching characteristics, driving circuit functionality, thermal management performance, insulation integrity, and sustained operation at full power. We utilized the double pulse test (DPT) to characterize switching performance in a two-level phase leg configuration, extract circuit parasitics, and validate magnetic components. The DPT was further applied to optimize gate driving circuits, validate overcurrent protection mechanisms, and measure device on-resistance. Additionally, a multicycle test was introduced to rapidly assess steady-state converter performance and estimate efficiency. Recognizing the critical role of thermal management in high-power converters, our methodologies extend to the experimental extraction of key thermal parameters—such as junction-to-ambient thermal resistance and thermal capacitance—via a heat loss injection method. A correlation method between temperature sensor measurements and junction temperature is presented to enhance the accuracy of device temperature monitoring during tests. To ensure reliability and safety, dielectric withstand tests and partial discharge measurements were conducted at both component and converter levels under conventional 60 Hz sinusoidal and high-frequency PWM waveforms. Finally, we highlight the importance of testing converters under full voltage, current, and thermal conditions through power circulating tests with minimal power consumption, applicable to both non-isolated and isolated high-power converters. Practical examples are provided to demonstrate the effectiveness and applicability of these hardware testing methodologies.

A novel thermal buffer utilizing dissolution heat to cooling electronic devices in isolated environment

A thermal buffer with high cooling capacity can rapidly absorb heat, preventing electronic devices in isolated conditions from overheating and extending their working time. This paper introduced the design of a thermal buffer featuring a meltable partition to utilize dissolution heat and conducted experimental investigations into the endothermic characteristics of CO(NH2)2 dissolving in water under different solute proportions, dissolving temperatures, and heat fluxes. The results demonstrated that natural convection was suppressed by the high viscosity of the CO(NH2)2 solution, preventing the cooling capacity of the thermal buffer from achieving the expected performance. Fortunately, the utilization efficiency of sensible heat was improved by movement and higher dissolving temperatures, significantly enhancing the cooling capacity. It should be noted that the cooling capacity of a thermal buffer filled with NH4NO3/H2O can surpass that of paraffin by >12 times at q = 1 W·cm−2 and tp = 70 °C, attributed to the advantages of the endothermic reaction, including a replaceable dissolving temperature, short dissolving time, and considerable dissolution heat. Moreover, these advantages are significantly amplified with increased heat flux and decreased operating temperatures of electronic devices. These insights deepen our understanding of the endothermic characteristics of solute dissolution in water, providing valuable guidance for designing thermal buffers with superior cooling capacity.

Micro-Channel Cooling of Hot Spots Through Non-Uniform Aspect Ratio Designs

Abstract Electronic devices experience spatial variation in power dissipation, which results in high-temperature hot spots. These locations require aggressive thermal management, which can be complex and costly. Simple solutions such as single-phase micro-channels can provide adequate heat transfer, but they are not designed to control heat transfer locally. However, micro-channels can be tailored to control local flow rates and heat transfer, potentially mitigating hot spot temperatures. Using a conductive and convective resistance network for a micro-channel, an analytical model is generated for heat transfer within an individual passage. For a given channel width, this model relates the channel depth to its resistance through a power law. Over a wide range of heat fluxes, the optimal design balances local temperatures to within 3 K. The analytical model is validated using computational simulations of the optimized heat sink. For a randomly-generated, non-uniform power distribution, device temperatures are balanced with a sample standard deviation below 2.5%, which is significantly better than a baseline design. When heat spreading is incorporated, the temperature increase is smaller but remains uniform, indicating that the hot spots can be mitigated.

Vortex Domain Wall Thermal Pinning and Depinning in a Constricted Magnetic Nanowire for Storage Memory Nanodevices.

In this study, we investigate the thermal pinning and depinning behaviors of vortex domain walls (VDWs) in constricted magnetic nanowires, with a focus on potential applications in storage memory nanodevices. Using micromagnetic simulations and spin transfer torque, we examine the impacts of device temperature on VDW transformation into a transverse domain wall (TDW), mobility, and thermal strength pinning at the constricted area. We explore how thermal fluctuations influence the stability and mobility of domain walls within stepped nanowires. The thermal structural stability of VDWs and their pinning were investigated considering the effects of the stepped area depth (d) and its length (λ). Our findings indicate that the thermal stability of VDWs in magnetic stepped nanowires increases with decreasing the depth of the stepped area (d) and increasing nanowire thickness (th). For th ≥ 50 nm, the stability is maintained at temperatures ≥ 1200 K. In the stepped area, VDW thermal pinning strength increases with increasing d and decreasing λ. For values of d ≥ 100 nm, VDWs depin from the stepped area at temperatures ≥ 1000 K. Our results reveal that thermal effects significantly influence the pinning strength at constricted sites, impacting the overall performance and reliability of magnetic memory devices. These insights are crucial for optimizing the design and functionality of next-generation nanodevices. The stepped design offers numerous advantages, including simple fabrication using a single electron beam lithography exposure step on the resist. Additionally, adjusting λ and d allows for precise control over the pinning strength by modifying the dimensions of the stepped areas.

Analysis of carrier dynamics and thermal effect of the GaAs photoconductive semiconductor switch in lock-on mode

Abstract The lock-on effect of the gallium arsenide photoconductive semiconductor switch (GaAs PCSS) at repetition rate aggravates the current crowding and electric field distortion, which significantly increases the risk of switch damage or even failure. Therefore, it is of great significance to investigate the carrier transport and the heat generation mechanism for improving the performance and longevity of GaAs PCSS in lock-on mode. The internal physical process of an opposed-electrode GaAs PCSS at low optical energy and strong electric field is analysed and discussed by experiment and simulation. A device-circuit hybrid simulation is employed to investigate the transient electric field, carrier concentration, and lattice temperature distribution within the GaAs PCSS in lock-on mode. The device temperature exhibits a positive correlation with the applied bias electric field, resulting in a peak temperature of 1037.25 K at an electric field of 38 kV/cm. The temperature distribution within the GaAs PCSS indicates a greater possibility for thermal breakdown and damage near the electrodes.

Diffusive Memristor with CuS Nanoparticles Embedded in Polymeric Film as Artificial Nociceptor.

The threshold behavior and the ion diffusion dynamics in diffusive volatile memristors have a very uncanny resemblance to the transduction process of biological nociceptors. Hence, the diffusive memristors are considered the most suited for making artificial nociceptive systems. To facilitate their widespread adoption, it is imperative to develop polymeric or organic-inorganic hybrid material-based diffusive memristors that are economical, biocompatible, and easily processable. In this study, we present a cluster-type polymeric diffusive memristor where copper is used as the active top electrode. The switching medium comprises copper(II) sulfide (CuS) nanoparticles embedded in poly(ethylene oxide) (PEO). The devices show electrochemical metalization (ECM)-type and bidirectional diffusive volatile memory with high nonlinearity (104) and turn-on slope (5.6 mV/dec). They reliably remain diffusive volatile with up to 10 wt % CuS in PEO and for a wide range of compliance (10-6 to 10-2 A) without transitioning to the bipolar nonvolatile type. The low reduction potential of CuS and optimal segmental dynamics of PEO work synergistically to ensure stable and reproducible diffusive memory. The CuS nanoparticles act as bipolar electrodes, undergoing local oxidation and reduction under the influence of the bias. The switching of resistance states in the CuS-PEO memristors is attributed to the formation of cluster-type filaments between CuS nanoparticles within the PEO matrix supported by the participation of copper ions from the top Cu electrode. The observation of low filament temperature and the independence of on-state resistance with respect to the device area and temperature further corroborate the cluster-type filament in CuS-PEO memristors. Using a 5 wt % CuS-based device, an artificial nociceptor is realized, which successfully mimics most of the nociceptive plasticities such as threshold, relaxation, no adaptation, and sensitization.

The effect of temperature variation on the transient response of RF PIN diode limiters for very high frequency applications

AbstractThis work presents the effect of temperature change on the capacitance of silicon PIN diodes and the resulting change in performance of RF limiters at very high frequency (VHF). Device temperatures were varied between −25 ºC and 100 ºC, with small‐signal parameters (including device capacitance) extracted at regular temperature increments and bias voltages from −20 Vdc to +3 Vdc using a multi‐bias parameter extraction method. It was found that the junction capacitance of the four PIN diodes under investigation increases with temperature, as expected from carrier lifetime behaviour, while results also confirmed prior observations of an inverse relationship between forward‐biased series resistance and temperature. Devices were subsequently tested in two different limiter topologies through high‐power transient measurements. It was found that the combination of increased capacitance and decreased resistance with increasing temperature increases the transient spike leakage and decreases the flat leakage of a limiter. It was also concluded that, for VHF, an anti‐parallel topology provides the best performance over a wide range of temperatures.

Energy Evaluation and Mathematical Modeling of Pellet Production from Metal-Bearing Waste with a Focus on Alternative Applications of Reducing Agents

The authors of this study focused on the energy and material assessment of processes for processing pellets from metal-bearing waste, specifically Fe concentrate. A mathematical model was created for process evaluation, with which thermotechnical calculations of parameters in the processing of metallized pellets were carried out. Thermodynamic calculations were performed to determine the enthalpy of the charge in individual devices (drying chamber, rotary kiln, cooler). For the reduction of Fe oxides, carbon from coke (with Fe oxide reductions of 50%, 61%, and 92%) and lignite (with Fe oxide reductions of 69% and 92%) were considered as part of the pellets. The degree of reduction of iron oxides was a determining parameter, and the consumption of the reducing agent corresponded to the direct reduction of Fe oxides by carbon with a coefficient of 1.5. Another determining parameter was the input and output temperature in individual devices. For a more precise description of the processes in individual devices, calculations were carried out zonally. The results of the calculations are analyses and recommendations for feasible alternatives for the reducing agent and associated processes.

GaAs quantum transport: Scrutinizing the effects of pressure, temperature and Rashba-Dresselhaus spin-orbit interactions for next-generation spintronic devices

This research investigates the spin-dependent transmission attributes and associated Giant Magnetoresistance (GMR) effect emerging from spin-polarized electron tunneling in a GaAs quantum well superlattice (QWS). The influence of Rashba and Dresselhaus spin-orbit interactions (SOIs) on transport properties is analyzed under the framework of the scattering matrix method. Our quantitative findings revealed that these spin-orbit couplings (SOCs) introduce inherent spin-filtering mechanisms, significantly influencing transmission probabilities. Furthermore, numerical estimations proved that external perturbations including pressure, temperature and structural modifications considerably impact the quantum transport characteristics of the scrutinized system. Additionally, major outcomes suggest that precise manipulation of spin-dependent transport in GaAs QWS holds promise for advancing spintronics technology. It is found that with well-tuned parameter values, the SOCs behave as a spin-dependent barrier modifying the band shape and its anisotropy. This study offers novel insights into the fundamental physics governing spin-dependent transport within quantum superlattices with promising implications for the development of advanced spintronic devices.

Research on performance of porous scaffold-based getter activated by induction heating and its application in MEMS device

Non-evaporable getter (NEG) is widely used in vacuum packaging. However, there are two main contradictions. Firstly, the contradiction between bonding temperature of the device and activation temperature of the getter results in the getter being activated first and then packaged, and cannot be repeatedly activated, which seriously reduces the adsorption capacity and life of the getter. Secondly, the contradiction between the small package volume and the large adsorption capacity, how to integrate large adsorption capacity getter in a small space is a tricky problem. In view of the above contradictions, a porous scaffold-based getter activated by induction heating was proposed in this paper, results show that when nickel plating is used as the induction heating layer, the temperature can quickly rise to 700 °C within 10 s, and 1 μm Ti getter can be fully activated for 7 min. The good periodicity of the temperature curves proved that the nickel layer has good repeatable heating characteristics. In addition, the adsorption performance of the getter was tested and characterized at device level. The device level characterization of optical deflection method proves the effectiveness of induction heating to activate getter, which lays a foundation for the application of getter on MEMS devices.

Numerical investigation on non-toxic double perovskites A2(BB′)X6 for all-inorganic efficient photovoltaics

Presently, the Bi-based 3D A2(BB′)X6 double perovskites (DPs) show an excellent photovoltaic (PV) performance with ambient stability compared to Pb-based counterparts. The structural, electronic, and optical properties analyses of A2BiCuX6 (A=Cs, Rb, K, X=I, Br, Cl) DPs are performed by CASTEP software, and the Cs2BiCuI6 is found to be the best suitable absorber among all of them. The density of states calculation reveals that Cu-3d and X-p orbitals are the major contributors to valence band maxima (VBM), whereas Bi-6p orbitals are responsible for the contribution to conduction band minima (CBM). Using SCAPS-1D simulation tool, the impact of variation in thickness, defect density, mobility of charge carriers, series resistance (RS), shunt resistance (RSh), and device temperature on PV performance of the device has been analysed. The optimised all inorganic FTO/WS2/Cs2BiCuI6/MXene/Pt structured device has provided an excellent PV performance i.e., PCE of 31.25 %, FF of 82.71 %, VOC of 1.24 V, and JSC of 30.40 mA/cm2 using 2D structured ETL (WS2) and HTL (MXene). This analysis provides an advanced understanding of cheap, environmentally stable, easily obtainable Bi-Cu based DP counterparts, which can be used in the fabrication of PV cells practically.