Temperature Polycrystalline Silicon Thin-film Transistors Research Articles

Investigating DC and AC degradation behaviors to P-type low temperature polycrystalline silicon thin film transistor with fin-like structure

Currently, thin film transistor (TFT) based on planar structure is widely used in the applications of display panels. However, when the device is scaling-down, new device structures or novel materials should be introduced. In this work, the low temperature polycrystalline silicon (LTPS) TFT with fin-like structure is investigated. On the basis of electrical measurements, the device features good switching characteristics with low operating voltages. However, the I d–V g sweeping result exhibits off-state leakage, which is known as the gate-induced drain leakage (GIDL) current. The GIDL current is increased with the drain bias and the temperature increasing. To observe the GIDL current degradations, different gate biases with negative bias stress and positive bias stress are applied. The results show different degradation behaviors. In addition, bias stresses with DC and AC methods are also applied to verify the device reliability. Both threshold voltage (V t) shift and sub-threshold swing (S.S.) are also extracted to verify the degradations of the device. Finally, the physical models are also proposed to illustrate the degradation behaviors of the LTPS device with a fin-like structure, which can be beneficial to future related development of LTPS-based devices.

Electrical Characteristics of Atmospheric-Pressure Plasma Enhanced Chemical Vapor Deposition Fabricated Indium-Gallium-Zinc-Oxide Thin-Film Transistors with In-Situ Hydrogenation and Neutral Beam Oxidation

Low temperature poly-crystalline silicon thin-film transistors (LTPS-TFTs) and indium-gallium-zinc-oxide TFTs (IGZO-TFTs) are potential candidates for future technology of various displays. Due to its simple manufacturing process, low cost and good uniformity, IGZO-TFTs have been developed as main stream display technology. From the viewpoint of device electrical characteristics, a-IGZO TFTs have better field-effect mobility (>10 cm2/V * s), larger Ion/Ioff ratio (>106), smaller subthreshold swing (S.S) and good stability. In this study, atmospheric-pressure PECVD (AP-PECVD) is used to deposit a-IGZO active layer, during the deposition process In-Situ hydrogenation is applied to enhance the layer characteristics. Also, the layer is then surface oxidation treated by neutral beam system (NBS). The optimal TFTs device characteristics is reached with In-Situ hydrogenation of H2 90 sccm, and surface oxidation of 400 W NBS treatment. The field-effect mobility is 34.05 cm2/V * s, threshold voltage is 1.74 V, subthreshold swing is 62 mV/decade, and current ratio Ion/Ioff is 2.04×107. Compared with conventional plasma, NBS used in this study provides charge-free plasma which could enhance device electric characteristics.

Influence of flexible substrate in low temperature polycrystalline silicon thin-film transistors: temperature dependent characteristics and low frequency noise analysis

The carrier transport of p-type low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) on flexible substrate has been intensively studied and compared to that on glass substrate in order to improve device performance. To investigate the origin of carrier transport on different substrates, temperature dependent characterizations are carried out for electrical device parameters such as threshold voltage (VTH), subthreshold swing (SS), on-current (Ion) and effective carrier mobility (μeff). The poly-Si grain size Lgrain and the barrier height EB between grain boundaries are well known to be the main parameters to determine transport in polycrystalline silicon and can be extracted based on the polycrystalline mobility model. However, our systemic studies show that it is not grain size but EB that has more influence on the degradation of LTPS TFT on flexible substrates. The EB of flexible substrate is roughly 18 times higher than glass substrate whereas grain size is similar for both devices on different substrates. Compared to the LTPS TFT on glass substrate, higher EB degrades approximately 24 % of Ion, 30 % of SS and 21 % of μeff on the flexible substrate at room temperature. From low frequency noise (LFN) analysis, it is observed that the total trap density (Nt) for flexible substrate is up to four times higher than that of glass substrate, which also supports the high value of EB in the device fabricated on the flexible substrate.

Investigation of the electromechanical stability of low temperature polycrystalline silicon thin-film transistors governed by types of stress

The electromechanical stability of low temperature polycrystalline silicon thin-film transistors embedded on plastic film was investigated as a function of type of stress and cyclic bending. The results show these devices to have reliable electromechanical integrity against mechanical strain at a bending radius of a few millimeters under compressive stress on the inner bending surface. By contrast, after being subjected to tensile stress on the outward bending surface, the devices show significant electrical failure under the induced strain. The onset of strain fracture also closely corresponds to the electrical failure of the device when exposed to tensile stress. The deformation kinetics caused by stress accumulation were investigated in multiple films with regard to a flexible backplane; these results reveal that mechanical integrity in reliable device design could be effectively provided by controlling the types of stress and could be put into practical use in flexible electronics applications.

Crack-guided effect on dynamic mechanical stress for foldable low temperature polycrystalline silicon thin film transistors

In the thin film transistors (TFTs) device research for foldable display, the degradation effect by the mechanical stress is crucial. Here, the crack position is critical for TFT reliability. However, it is difficult to characterize the crack position due to the random generation of the crack by mechanical stress. In this paper, the crack-guided low temperature polycrystalline silicon (LTPS) TFT test structures are fabricated and the crack-guided effects on mechanical stress of the tested TFT structure are analyzed. To strain on the foldable LTPS TFTs, 50,000cycles of tensile and parallel direction dynamic mechanical stresses were applied with 2.5-mm bending radius. Based on the results, the generating crack position can be guided and controlled and also TFT reliability for foldable display can be enhanced.

Abnormal Output Characteristics of p-Type Low Temperature Polycrystalline Silicon Thin Film Transistor Fabricated on Polyimide Substrate

We report on an abnormal output characteristics in p-type low temperature polycrystalline silicon thin-film transistors fabricated on polyimide (PI); negative differential conductance behavior is often observed in saturation region of drain current from large width devices. To understand such abnormal output characteristics, device dimension dependence was studied in a systematic way. As a result, we found that enhanced self-heating is mainly responsible originating from the poor thermal conductivity of PI substrate. A related degradation model is also proposed.

A Novel p-Type LTPS TFT Pixel Circuit Compensating for Threshold Voltage and Mobility Variations

In this paper, we propose a novel voltage programmed pixel circuit with p-type low temperature polycrystalline silicon thin-film transistors (LTPS TFTs) for active-matrix organic light-emitting displays (AMOLEDs) with an enhanced electrical stability and uniformity. Through extensive numerical analysis based on experimental data of p-type LTPS TFT and OLED, we confirm that the proposed pixel circuit can compensate for both the mobility variation and threshold voltage shift of TFTs.

P-채널 다결정 실리콘 박막 트랜지스터의 문턱전압 변동을 보상할 수 있는 5-TFT OLED 화소회로

본 논문에서는 p-채널 저온 다결정 실리콘 박막 트랜지스터의 문턱전압 변동을 보상할 수 있는 새로운 OLED 화소회로를 제안하였다. 제안한 5-TFT OLED 화소회로는 4개의 스위칭 박막 트랜지스터, 1개의 OLED 구동 박막 트랜지스터 및 1개의 정전용량으로 구성되어 있다. 제안한 화소회로의 한 프레임은 초기화 구간, 문턱전압 감지 및 데이터 기입 구간, 데이터 유지 구간 및 발광 구간으로 나누어진다. SmartSpice 시뮬레이션 결과, 구동 트랜지스터의 문턱전압이 <TEX>${\pm}0.25V$</TEX> 변동 시 최대 OLED 전류의 오차율은 -4.06%이였고 구동 트랜지스터의 문턱전압이 <TEX>${\pm}0.50V$</TEX> 변동 시 최대 OLED 전류의 오차율은 9.74%였다. 따라서 제안한 5T1C 화소회로는 p-채널 다결정 실리콘 박막 트랜지스터의 문턱전압 변동에 둔감하여 균일한 OLED 전류를 공급함을 확인하였다. This paper proposes a novel OLED pixel circuit to compensate the threshold voltage variation of p-channel low temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed 5-TFT OLED pixel circuit consists of 4 switching TFTs, 1 OLED driving TFT and 1 capacitor. One frame of the proposed pixel circuit is divided into initialization period, threshold voltage sensing and data programming period, data holding period and emission period. SmartSpice simulation results show that the maximum error rate of OLED current is -4.06% when the threshold voltage of driving TFT varies by <TEX>${\pm}0.25V$</TEX> and that of OLED current is 9.74% when the threshold voltage of driving TFT varies by <TEX>${\pm}0.50V$</TEX>. Thus, the proposed 5T1C pixel circuit can realize uniform OLED current with high immunity to the threshold voltage variation of p-channel poly-Si TFT.

Voltage‐programmed AM‐OLED pixel circuit to compensate threshold voltage and mobility variations

A novel voltage-programmed pixel circuit is proposed to achieve an active-matrix organic light-emitting display (AM-OLED) based on a low temperature polycrystalline silicon thin-film transistor (TFT) with an enhanced electrical stability and uniformity. The proposed pixel circuit consists of one driving TFT, one setup TFT, four switching TFTs, one capacitor, and four control signal lines. Through an extensive simulation work based on the HSPICE tool, it has been verified that the proposed pixel circuit can compensate for both mobility variations and threshold voltage shifts of the driving TFT.

A new LTPS TFT AC pixel circuit for an AMOLED

This work presents a new voltage programmed pixel circuit for an active-matrix organic light-emitting diode (AMOLED) display. The proposed pixel circuit consists of six low temperature polycrystalline silicon thin-film transistors (LTPS TFTs), one storage capacitor, and one OLED, and is verified by simulation work using HSPICE software. Besides effectively compensating for the threshold voltage variation of the driving TFT and OLED, the proposed pixel circuit offers an AC driving mode for the OLED, which can suppress the degradation of the OLED. Moreover, a high contrast ratio can be achieved by the proposed pixel circuit since the OLED does not emit any light except for the emission period.

A low‐cost and reliable optical inspection system for rapid surface roughness measurements of polycrystalline thin films

AbstractExcimer laser crystallization is a well‐known industrially used technique to produce high‐performance polycrystalline silicon thin films on the commercially available inexpensive glass substrates for the development of high‐performance low temperature polycrystalline silicon thin‐film transistors in active matrix flat panel displays. A rapid optical measurement system for rapid surface roughness measurement of polycrystalline silicon thin films was developed in this study. Two kinds of thicknesses of polycrystalline silicon thin films were used to study rapid surface roughness measurements. Six different incident angles were employed for measuring surface roughness of polycrystalline silicon thin films. The results reveal that the incident angle of 20° was found to be a good candidate for measuring surface roughness of polycrystalline silicon thin films. Surface roughness (y) of polycrystalline silicon thin films can be determined rapidly from the average value of reflected direct current voltage (x) measured by the optical system developed using the trend equation of y = –8.9854x + 91.496. The maximum measurement error rate of the optical measurement system developed was less than 5.72%. The savings in measurement time was up to 83%.

Illumination-Assisted Negative Bias Temperature Instability Degradation in Low Temperature Polycrystalline Silicon Thin-Film Transistors

In this work, the negative bias temperature instability (NBTI) in low temperature polycrystalline silicon thin-film transistors in a darkened and in an illuminated environment was investigated. Experimental results reveal that the generation of interface state density (N it ) showed no change between the different NBTI stresses. Nevertheless, the degradation of the grain boundary trap (N trap ) under illumination was more significant than that in the darkened environment. This phenomenon is mainly caused by the extra number of holes generated during the illuminated NBTI stress.

Reliability of Low Temperature Polycrystalline Silicon Thin-Film Transistors with Ultrathin Gate Oxide

We analyzed the reliability against the hot-carriers effect and Joule heating effects of low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with an ultrathin gate oxide film deposited by sputtering. For the hot-carrier effect, although the generation of hot-carriers was enhanced in TFT with a thin gate oxide film, no marked degradation due to direct constant voltage (DC) stress was observed in the electric characteristics even when the thickness of the gate oxide film was 9.5 nm. Regarding the effect of Joule heating on the reliability, the thickness of the oxide film markedly affected the TFT characteristics. A new degradation mode different from the conventional mode with a shift in threshold voltage owing to heat generation was observed when the oxide film was extremely thin in spite of small amount of heat generated during the application of DC stress. Regarding the reliability of the low-temperature poly-Si TFT with an ultrathin gate oxide film, the results revealed that a new degradation mode develops due to heat generation.

Performance Improvement of Ultralow Temperature Polycrystalline Silicon TFT on Plastic Substrate by Plasma Oxidation of Polycrystalline Si Surface

The thin-film transistor (TFT) performances were enhanced and stabilized by the plasma oxidation of the polycrystalline Si surface prior to the plasma enhanced atomic layer deposition of an Al2O3 gate dielectric film. The authors attribute this improvement to the formation of a high-quality oxide interface layer between the gate dielectric film and the poly-Si film. The interface oxide has a predominant effect on the TFT's characteristics and is regulated by the plasma oxidation temperature and the gap distance between the electrode and polycrystalline Si surface

Characteristics and stress-induced degradation of laser-activated low temperature polycrystalline silicon thin-film transistors

The characteristics and reliability of laser-activated polycrystalline silicon thin-film transistors (poly-Si TFTs) under the stress condition of drain voltage (Vd)=12 V and gate voltage (Vg)=15 V have been investigated. In spite of reducing the source/drain resistivity by using laser activation method, the leakage current (Vg&amp;lt;0) is larger for laser-activated poly-Si TFTs in comparison with traditional furnace-activated counterparts. It is also found that the post-stress leakage and on/off current ratio degrade much faster for laser-activated poly-Si TFTs, while the degradation rates of threshold voltage and subthreshold swing are comparable to those of traditional furnace-activated TFTs. The laser activation modifies the grain structure between drain and channel region and causes grain discontinuity extending from the drain side to the channel region. The grain discontinuity near drain side in the polysilicon film has been investigated by transmission electron microscopy analysis. The effective trap state density calculated from typical I−V curve has been compared for laser-activated and furnace-activated TFTs. As a result, an inferior reliability with extra trap state density and larger leakage current was observed in the laser-activated poly-Si TFTs.