Fault Tolerance Techniques Research Articles

A systematic review of fault tolerance techniques for smart city applications

Smart City Applications encompass many characteristics that increase the risk of failures, such as context-awareness, adaptiveness, distribution and heterogeneity. Therefore, it is important to implement fault-tolerant mechanisms to produce more reliable applications. This study presents a systematic literature review of fault tolerance techniques that have been proposed for, or applied to Smart City Applications. It also characterizes faults, errors and failures that may occur in these systems. To the best of our knowledge, this is the first review that provides a broad picture of the research area and points out research limitations and directions. We selected 43 primary studies and performed initial classifications (e.g., based on type of research, type of contribution, application domains and subdomains, and type of system architecture). We further classified and discussed the selected studies based on types of fault tolerance techniques and types of faults and failures. System Reconfiguration, Diversity, and Retry are classical techniques that have been investigated in this domain. Many fault and failure types have also been addressed. While those well-known techniques have been explored for introducing fault tolerance capabilities into Smart City Applications, others have been overlooked. Moreover, evidence on the effectiveness and applicability of the proposed fault tolerance solutions is still very limited.Editor’s note: Open Science material was validated by the Journal of Systems and Software Open Science Board.

Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability

An essential consideration in processor design is ensuring reliability, particularly in demanding environments such as outer space and nuclear plants. To mitigate the effects of errors and enable error recovery, processors need to incorporate fault tolerance techniques. One common type of error is SEU (Single Event Upset), which affects various microelectronic devices including microprocessors, microcontrollers, and semiconductor memory devices. While error mitigation techniques have been developed for processors based on architectures like ARM (Advanced RISC Machine) and MIPS (Million Instructions Per Second), there is a gap in research for open-source ISAs (Instruction Set Architecture) like RISC-V, which this paper aims to address. This paper focuses on designing a fault-tolerant microarchitecture for a RISC-V processor that can correct one-bit errors, detect up to two-bit errors, and integrate lockstep and pipeline rollback features at a lower LUTs (Look Up Tables) consumption by re-using the same hardware pipeline for error mitigation and recovery through instruction mimicking. By incorporating these features, the proposed approach enhances the system’s fault tolerance by detecting and correcting errors caused by transient events and achieves a lower effective die size upon realization compared to contemporary works. The proposed microarchitecture design was simulated and synthesized using the Vivado Design Suite 2023.1 and implemented on a Zynq 7000 SoC ZC702 Evaluation Kit.

Blockchain-Based LSTM Approach for Secure Data Transmission in IoT-Enabled Healthcare System

Blockchain technology can help with a number of issues facing the healthcare sector. Its potential as trust brokers includes the provision of incentive machines and the facilitation of innovative healthcare solutions. Additionally, its potential as trust brokers includes the facilitation of novel business models that offer fresh perspectives on the interactions between patients and providers, among other diverse healthcare stakeholders. Blockchain, for instance, makes incentive structures easier to implement and promotes decentralised trust in patient-centered healthcare models and global health information exchange (HIE). On the other hand, blockchain is characterised as a decentralised network or service that can help remove obstacles in the healthcare sector. The healthcare sector has benefited greatly from the effective resolution of problems relating to adoption and technological obstacles, interoperability and integration with current systems, cost unpredictability, scale, and regulatory compliance through the use of Blockchain technology. This work proposed discusses fault tolerance techniques in relation to sharing health-related data.

Fault-Tolerant Technique Against Current Sensors for Model Predictive Control of Induction Motor Drives

Fault-Tolerant Technique Against Current Sensors for Model Predictive Control of Induction Motor Drives

Priority-based fault tolerance mechanism with neighbour candidate node discovery algorithm and task processing by replication and forwarding technique under Fog-IoT wireless computing environments

The real-world exponential increase in data traffic has brought attention to a new computing paradigm termed Fog Computing (FC), which is intended for task offloading in fault-free fog networks. It is a potential aid which that provides greater processing aids at lower costs and with greater availability, flexibility, and cost. The issue typically arises due to the high task count and impacts task offloading in fog scenarios. In order to address a problem that arises in the Fog-IoT network for providing dependable and error-free transmission, an appropriate technique is required. Based on fault minimization and cost optimisation, the novel FT mechanism is proposed in this research. First, proposed Priority based Task offloading with Fault Tolerance (PToFT) scheme is used to identify the faulty-FNs using FN's remaining residual energy. To find the neighbour candidate Fog access node for replacing the faulty-FNs, the Min-cost Neighbour Candidate Node Discovery based on replication and forwarding (MNCND-RaF) technique is proposed for effective task processing and also tracks the task information towards the new nodes. These proposed methods are simulated, evaluated, and compared with the current Fault Tolerance (FT) techniques. The results shows that the compared results of the proposed methods will outperforms with current approaches like Without FT, NFT-WOA, and DFTLA methods, as 42.3 %, 36.2 %, and 27.7 %, respectively. Additionally, it utilized 1.53 J of residual energy as compared with HBI-LB and 0.84 J without replicas.

Distributed consensus and formation control of multi-AUV systems under actuator faults and switching topology

This note presents the distributed consensus and formation control for a group of AUVs, comprising one leader and three followers arranged in a diamond formation. The study addresses significant control challenges, including external disturbances, noise, model uncertainties, actuator faults, stochastic switching topologies, time-varying communication delays, and positional information between agents. Stochastic switching topologies are assumed to follow a Markov chain. To effectively address these challenges and ensuring satisfactory performance levels, two control architectures have been formulated to facilitate the imposition of desired trajectories upon the system states. The initial architecture amalgamates sliding mode control methodology with adaptive algorithms, designed explicitly for tracking missions in the presence of fully functional actuators. In response to potential actuator failures, the second control architecture integrates passive fault-tolerant techniques, significantly enhancing system reliability under such circumstances as well as switching topology. The proposed framework demonstrates its effectiveness in managing the high nonlinearity and coupled dynamics of AUVs. Simulation results validate the efficacy of the developed strategy. It successfully establishes a desired consensus and formation among agents, reduces chattering phenomena, accurately tracks reference trajectories, handles disturbances and uncertainties within an unknown domain, and achieves finite-time convergence.

An Investigative Study on Fault-Tolerant Design Principles for Future Internet

Fault tolerance is crucial for ensuring uninterrupted service delivery in future internet architectures. This paper presents an investigative study on fault-tolerant design principles tailored to the evolving needs of future internet systems. Beginning with a comprehensive review of existing fault tolerance techniques in current internet architectures, the study identifies the limitations and challenges traditional approaches face in meeting the requirements of future internet environments. Fundamental concepts of fault tolerance are discussed, including fault types, detection mechanisms, and recovery strategies. Essential requirements and challenges for future internet architectures are identified, encompassing scalability, heterogeneity, dynamicity, security, and resource constraints. Building upon this foundation, the paper presents a set of comprehensive fault-tolerant design principles customized for future internet systems. These principles address architectural considerations, fault detection and isolation mechanisms, and recovery strategies. Case studies and real-world examples illustrate the application of these design principles in large-scale internet platforms and distributed systems. The paper outlines future research directions and opportunities for further innovation in fault-tolerant design for future internet architectures.

Proactive Fault Tolerance in Distributed Cloud Systems: A Review of Predictive and Preventive Techniques

In a cloud computing environment, various hardware and software services are provided to the users across multiple servers and data centers. These servers are communicated to each other to allow greater scalability, flexibility, and reliability. Reliability is a vital factor in cloud computing that ensures that the requested services will be delivered to the users whenever they request them. However, different hardware or software faults may occur in cloud servers or data centers that prevent the users from receiving the service. Fault tolerance is defined as the ability of the system to provide services to the users even with the presence of faults or failures. In this review, we focused on some of the emerging fault tolerance techniques researchers have proposed to tackle the fault issues in cloud computing. We divided these techniques into three main categories: proactive and reactive techniques. Proactive techniques involve protecting the system defects by proposing certain procedures to prevent reaching the defective condition. Reactive techniques refer to the ability of the cloud system to recover the defective server or framework to continue working and providing the service.

LEC-MiCs: Low-Energy Checkpointing in Mixed-Criticality Multi-Core Systems

With the advent of multicore platforms in designing Mixed-Criticality Systems (MCSs), simultaneous management of reliability and energy while guaranteeing an acceptable service level for low-criticality tasks is a crucial challenge. To ensure the reliability of the MCSs against transient faults, fault-tolerant techniques are employed which will increase energy consumption. To mitigate the energy overhead, the Dynamic Voltage and Frequency Scaling (DVFS) technique will be exploited. However, this technique might lead to violating the timing constraints of high-criticality tasks. Therefore, this paper presents, for the first time, the low-energy checkpointing technique to guarantee the reliability of multiple preemptive periodic mixed-criticality tasks in a multicore platform. In contrast to the previous works in checkpointing technique which consider a specific number of faults that all the tasks in the system should tolerate, in this paper, the number of tolerable faults for each execution section of a task, and in each voltage and frequency level is determined through proposed formulas to meet the reliability target based on safety standards. Then, our proposed method determines the number of checkpoints and their non-uniform intervals for the normal and overrun sections of each task to reduce energy consumption, respectively. Moreover, the unified demand bound function (DBF) analysis is proposed for analyzing the schedulability of the task set, where each high-criticality task meets its timing and reliability constraints, and low-criticality tasks execute based on their derived guaranteed periods in each operational mode of the system. Experimental results show that our proposed scheme meets the timing and reliability constraints while at the same time, improving the QoS of low-criticality tasks, and managing energy consumption with an average of 29.49%, and 32.78%, respectively.

Fault Detection and Tolerance in Wireless Sensor Networks: A Study on Reliable Data Transmission using Machine Learning Algorithms

This research addresses the challenge of enhancing fault detection and tolerance in wireless sensor networks (WSNs) to ensure reliable data transmission in adverse conditions. Through simulation, experimentation, and modeling, the study develops techniques and algorithms for improving WSN fault resilience. Key evaluation criteria include Detection Accuracy, Response Time, Energy Efficiency, and Scalability. Redundancy-based methods, such as node and path redundancy, are explored as effective fault tolerance techniques. Results demonstrate lower response times, improved detection accuracy, energy efficiency, and scalability. The findings contribute to WSN technology by enhancing data accuracy, network resilience, and energy conservation, though challenges and limitations persist.

A Review on the Fault-Tolerant Method of PMSM using Finite Element Method by Modifying Phase Angle for EV Applications

Abstract: The present research reviews a fault-tolerant technique for Permanent Magnet Synchronous Motors (PMSMs) that involves phase angle adjustment. Fault tolerance standards for the motor used in electric vehicles are necessary due to the rapid development of these vehicles. The primary option for electric vehicle drive motors is increasingly being replaced with permanent magnet synchronous motors (PMSM), which have minimal torque ripple, great durability, and other benefits. After comparing a six-phase PMSM to a conventional three-phase PMSM, the performance following a phase open is examined. A fault-tolerant technique for modifying the left phase current's phase angle to reduce torque ripple following a phase open is then described. The finite element simulation indicates that the six-phase PMSM's output torque ripple is reduced, and the fault-tolerant technique that is being described can further reduce the torque ripple.

Markov chain‐based analysis and fault tolerance technique for enhancing chain‐based routing in WSNs

SummaryWireless sensor networks (WSNs) are faced with the challenge of energy conservation, which makes efficient routing protocols crucial for prolonging network lifetime. In addition, delay time from sensors to the base station is critical in applications such as military, medical, and security monitoring systems. Chain‐based protocols like PEGASIS, CCBRP, and CCM have been developed to address routing in WSNs, with the aim of reducing energy consumption and delay. However, node failures are inevitable due to energy reduction and node mobility. Therefore, fault tolerance techniques must be integrated into routing protocols. A new fault tolerance method has been proposed to prevent early chain failures in WSNs by formulating network availability and reliability using Markov chain analysis. The results indicate that chain‐based routing protocols with one spare node are more reliable than those with two spare nodes.

Fault tolerance challenges in wearable computing for vital applications: a survey

Wearable computers can be used in different domains including healthcare. However, due to suffering from challenges such as faults their applications may be limited in real practice. So, in designing wearable devices, designer must take into account fault tolerance techniques. This study aims to investigate the challenging issues of fault tolerance in wearable computing. For this purpose, different aspects of fault tolerance in wearable computing namely hardware, software, energy, and communication are studied; and state of the art research regarding each category is analysed. In this analysis, the performed works using the fault tolerance techniques are included in the form of 25 components and referred to as “fault tolerance plan”. Using this fault tolerance plan and the appropriate profile, the fault tolerance of any wearable system can be evaluated. In this article, fault tolerances of several of the most prominent works conducted in the field of wearable computing were evaluated. The obtained results, with the medical profile, showed that only one wearable system had a fault tolerance of 91%, with the other systems having a fault tolerance of 24% or less. Also, the results obtained from evaluating these works, with the military profile, showed that only one wearable system had a fault tolerance of 76%, with the other systems having a fault tolerance of 19% or less. These mean that few studies have been conducted on the fault tolerance of wearable computing.

An Open-Circuit Fault Diagnosis Method for LLC Converters

In electrified transportation systems, power system failures can lead to greater disasters. Therefore, the reliability of converters in transportation systems has been a concern. Fault-tolerant techniques are widely applied to ensure that converters can continue to supply loads under fault conditions. Fault diagnosis as a prerequisite for fault tolerance has also become a research hotspot. This paper proposes a fast method for fault diagnosis of high-frequency LLC converters. The proposed fault diagnosis method is based on the observation of the voltage across the resonant capacitor to determine and locate the faulty power switch, providing a basis for fault tolerance. This diagnosis method requires a voltage sensor, which is also necessary for some control methods. When applying these control methods, the proposed fault diagnosis method can be used without additional sensors, beneficial for cost reduction. A full-bridge LLC converter controlled by a digital signal processor was used as an experimental platform to verify the effectiveness and speed of the proposed diagnostic method. The results show that the proposed fault diagnosis method can achieve the fast diagnosis of high-frequency LLC converters in a short time and with only minimal computational resources.

FPGA-Accelerated Erasure Coding Encoding in Ceph Based on an Efficient Layered Strategy

Distributed storage systems such as Ceph have been widely adopted, with erasure coding technology being an essential fault-tolerance technique. While ensuring data reliability and security, it significantly reduces the cost of data storage. Due to the computational overhead and encoding latency introduced by the erasure coding process, the data encoding rate is often constrained. To address this issue, an FPGA-accelerated erasure coding encoding scheme in Ceph, based on an efficient layered strategy (FPGA-Accelerated Erasure Coding Encoding in Ceph with an Efficient Layered Strategy, LFEC-Accelerator), is proposed and implemented. This approach takes full advantage of FPGA’s parallel computing capabilities to accelerate the erasure coding algorithm at the hardware level. Furthermore, to maximize the utilization of the FPGA controller’s resources and ensure that all processing steps are properly managed and scheduled, our approach introduces a hierarchical structure comprising a communication interface layer, task scheduling layer, and hardware acceleration layer. Experimental results indicate that, under the same erasure coding configurations and file sizes, our solution outperforms native Ceph-supported erasure coding libraries such as Jerasure, Clay, Shec and ISA, with an encoding rate improvement of up to 3.04 times.

Design analysis of moth-flame optimized fault tolerant technique for minimally buffered network-on-chip router

<span>A network on a chip is a solitary silicon chip utilized to perform the communication characteristics of large-scale (LSI) to very large-scale integration (VLSI) systems. Network-on-chip (NoC) architecture includes links, network interfaces (NI), and routers to unite with external memories or processors. NoC is designed to flow messages from the source module to the destination module through several links involving routing decisions. <br /> The design of NoC is complex and the buffer section’s expensiveness creates problems while providing secured data service. Moreover, routers and links in NoC setups are liable to faults. This work introduces a minimal buffered router, and the faults in the network are optimized using moth flame optimized (MFO) fault-tolerant technique. The software named Xilinx ISE design suite 14.5 is employed for the minimum buffered router model. <br /> The suggested scheme is operated with less area, low power (0.241 mW), and high speed (965.261 Megahertz (MHz)) when matched with previous works.</span>

Energy Efficient Task Scheduling Using Fault Tolerance Technique for IoT Applications in Fog Computing Environment

Energy Efficient Task Scheduling Using Fault Tolerance Technique for IoT Applications in Fog Computing Environment

Partial Network Partitioning

We present an extensive study focused on partial network partitioning. Partial network partitions disrupt the communication between some but not all nodes in a cluster. First, we conduct a comprehensive study of system failures caused by this fault in 13 popular systems. Our study reveals that the studied failures are catastrophic (e.g., lead to data loss), easily manifest, and are mainly due to design flaws. Our analysis identifies vulnerabilities in core systems mechanisms including scheduling, membership management, and ZooKeeper-based configuration management. Second, we dissect the design of nine popular systems and identify four principled approaches for tolerating partial partitions. Unfortunately, our analysis shows that implemented fault tolerance techniques are inadequate for modern systems; they either patch a particular mechanism or lead to a complete cluster shutdown, even when alternative network paths exist. Finally, our findings motivate us to build Nifty, a transparent communication layer that masks partial network partitions. Nifty builds an overlay between nodes to detour packets around partial partitions. Nifty provides an approach for applications to optimize their operation during a partial partition. We demonstrate the benefit of this approach through integrating Nifty with VoltDB, HDFS, and Kafka.

Power-Efficient and Aging-Aware Primary/Backup Technique for Heterogeneous Embedded Systems

One of the essential requirements of embedded systems is a guaranteed level of reliability. In this regard, fault-tolerance techniques are broadly applied to these systems to enhance reliability. However, fault-tolerance techniques may increase power consumption due to their inherent redundancy. For this purpose, power management techniques are applied, along with fault-tolerance techniques, which generally prolong the system lifespan by decreasing the temperature and leading to an aging rate reduction. Yet, some power management techniques, such as Dynamic Voltage and Frequency Scaling (DVFS), increase the transient fault rate and timing error. For this reason, heterogeneous multicore platforms have received much attention due to their ability to make a trade-off between power consumption and performance. Still, it is more complicated to map and schedule tasks in a heterogeneous multicore system. In this paper, for the first time, we propose a power management method for a heterogeneous multicore system that reduces power consumption and tolerates both transient and permanent faults through primary/backup technique while considering core-level power constraint, real-time constraint, and aging effect. Experimental evaluations demonstrate the efficiency of our proposed method in terms of reducing power consumption compared to the state-of-the-art schemes, together with guaranteeing reliability and considering the aging effect.

A novel enhanced deep learning-based fault diagnosis approach for cascaded multilevel inverter

With the widespread use of power electronic converters like Multilevel Inverters (MLI) in various applications, several challenges arise due to increased switch count, capacitor surge current, and reverse current from inductive loads. These factors lead to the onset of faults, which negatively affect the reliability of MLI. Hence, an efficient fault detection and fault tolerant technique are necessary to ensure the reliability of the inverter. The deep learning-based fault detection approach is proposed for a 15-level Cascaded H-Bridge (CHB) MLI to address this issue. The proposed technique involves pre-processing with an Adaptive Hilbert-Huang filter, segmentation using Partial Differential Equation (PDE), feature extraction using Scale-Invariant Feature Transform (SIFT), and classification of fault signals with a Crow Swarm Algorithm (CSA) optimized Convolution Neural Network (CNN) classifier. To evaluate the effectiveness of the proposed approach in fault classification, four complex fault types were considered using MATLAB. The results show that CSA-optimized CNN offers a remarkable classification accuracy of 99.84%.