Worst-case Execution Time Of Tasks Research Articles

Prioritized Time-Point-Interval Petri Nets Modeling Multiprocessor Real-Time Systems and TCTL$_{x}$

When a group of real-time tasks with dependent relations are performed in parallel in a multi-processor interruptible environment, time-related requirements are easily destroyed so that the correct design of such a system is complex and difficult. Therefore, it is necessary for designers to use some precise methods to verify their correctness, while model checking based on time Petri nets and timed computation tree logic (TCTL) is such an effective method. However, the existing models and tools only focus on those multi-processor real-time systems where the number of processors of the same type is just one, and thus they cannot work for the case that the number of processors of the same type is greater than one. Hence, this paper proposes prioritized time-point-interval Petri nets (PToPN) to deal with it and defines their firing rules and state graphs to represent their behaviors. A PToPN can explicitly model the preemptive scheduling of such a real-time system, and TCTL formulas specifying design requirements of the system can be verified based on its state graph. Besides, we propose TCTL with unknown time bounds, denoted as TCTL <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$_{x}$</tex-math></inline-formula> , to compute the minimum or maximum time bound ensuring a related formula holds. Such a quantitative analysis is very necessary in the real applications because they can be used to compute some performances of a system such as the worst-case execution time of tasks and the idle time of processors. We design the related algorithms and develop a tool. We use a real example from HUAWEI Company to show the usefulness of our method, and do some experiments to show the advantages of our method compared with another state-of-the-art one.

Accounting for Preemption and Migration Costs in the Calculation of Hard Real-Time Cyclic Executives for MPSoCs

This work introduces a methodology to consider preemption and migration overhead in hard real-time cyclic executives on multicore architectures. The approach performs two iterative stages. The first stage takes a cyclic executive, from which the number and timing of all preemptions and migrations for every task is known. Then, it includes this overhead by updating the worst-case execution time (WCET) of the tasks. The second stage calculates a new cyclic executive considering the new WCET of tasks. The stages iterate until the preemption and migration overhead keeps constant.

Isolation scheduling on multicores: model and scheduling approaches

Deploying real-time applications on multicores is challenging because tasks that are executed concurrently on different cores can interfere on shared resources, severely complicating worst-case timing analysis. To tackle this challenge, we propose a new scheduling model called isolation scheduling (IS): IS provides a framework to exploit multicores for real-time applications where tasks are grouped into classes. IS enforces mutually exclusive execution among different task classes, thus eliminating inter-class interference by construction. We assume that interference due to the statefulness of shared resources is either negligible or accounted for in the worst-case execution time of tasks. Mixed-criticality systems provide an example where IS is applicable. We propose and analyze two novel approaches for isolation scheduling: a global approach based on fluid scheduling and a partitioned approach based on hierarchical server scheduling, each with extensions to mixed-criticality applications. Through extensive simulations, we compare the two approaches in terms of schedulability and runtime overheads and quantify the schedulability loss due to the isolation constraint. Moreover, we conduct a comparative study among state-of-the-art approaches that comply with our IS model, showing that the new approaches can significantly outperform existing ones in terms of schedulability.

Combining loop unrolling strategies and code predication to reduce the worst-case execution time of real-time software

Worst-case execution time (WCET) is a parameter necessary to guarantee timing constraints on real-time systems. The higher the worst-case execution time of tasks, the higher will be the resource demand for the associated system. The goal of this paper is to propose a different way to perform loop unrolling on data-dependent loops using code predication targeting WCET reduction, because existing techniques only consider loops with fixed execution counts. We also combine our technique with existing unrolling approaches. Results showed that this combination can produce aggressive WCET reductions when compared with the original code.

SPACE: Semi-Partitioned CachE for Energy Efficient, Hard Real-Time Systems

Multi-core processors are increasingly popular because they yield higher performance, but they also present new challenges for hard real-time systems in that they make it much more difficult to estimate a task's worst-case execution time (WCET). Partitioned cache architecture is being used to ease the problem by providing an isolated execution environment for each thread. Although simple to implement and use, this method may be sub-optimal with respect to both energy consumption and performance since it prevents taking advantage of information shared across threads for both instructions and data. This work presents a new cache architecture termed SPACE (Semi-Partitioned CachE) that makes it possible to leverage information sharing, yielding in turn a tighter WCET. The SPACE architecture together with our new WCET algorithm can be used to maintain the predictability of the execution time of the parallel threads while reducing the overall energy consumption of the system. The new proposed cache architecture was implemented using Verilog and deployed on a Xilinx MicroBlaze multi-core design for testing, validation and measurements. The application level experiments were conducted using the Chronos tool for estimation and the Wattch/SimpleScalar simulator for execution. Using three real-time programs–a radar tracker, a DES encryption algorithm, and an FM radio–we showed that SPACE together with the enhanced WCET algorithm reduce the average system WCET of these applications by 31 percent and reduce the actual energy consumption by 18 percent in comparison with other cache architectures.

Fault-Tolerant Task Scheduling for Mixed-Criticality Real-Time Systems

Integration of safety-critical tasks with different certification requirements onto a common hardware platform has become a growing tendency in the design of real-time and embedded systems. In the past decade, great efforts have been made to develop techniques for handling uncertainties in task worst-case execution time, quality-of-service, and schedulability of mixed-criticality systems. However, few works take fault-tolerance as a design requirement. In this paper, we address the scheduling of fault-tolerant mixed-criticality systems to ensure the safety of tasks at different levels of criticalities in the presence of transient faults. We adopt task re-execution as the fault-tolerant technique. Extensive simulations were performed to validate the effectiveness of our algorithm. Simulation results show that our algorithm results in up to [Formula: see text] and [Formula: see text] improvement in system reliability and schedule feasibility as compared to existing techniques, which contributes to a more safe system.

A Survey on Cache Management Mechanisms for Real-Time Embedded Systems

Multicore processors are being extensively used by real-time systems, mainly because of their demand for increased computing power. However, multicore processors have shared resources that affect the predictability of real-time systems, which is the key to correctly estimate the worst-case execution time of tasks. One of the main factors for unpredictability in a multicore processor is the cache memory hierarchy. Recently, many research works have proposed different techniques to deal with caches in multicore processors in the context of real-time systems. Nevertheless, a review and categorization of these techniques is still an open topic and would be very useful for the real-time community. In this article, we present a survey of cache management techniques for real-time embedded systems, from the first studies of the field in 1990 up to the latest research published in 2014. We categorize the main research works and provide a detailed comparison in terms of similarities and differences. We also identify key challenges and discuss future research directions.

측정기반 최악실행시간 분석 기법을 이용한 AUTOSAR 호환 승용디젤엔진제어기의 실시간 성능 검증에 관한 연구

In this study, we presented a timing verification method for a passenger car diesel engine management system (EMS) using measurement-based worst-case execution time (WCET) analysis. In order to cope with AUTOSAR-compliant software architecture, a development process model is proposed. In the process model, a runnable is regarded as a test unit and its temporal behavior (i.e. maximum observed execution time, MOET) is obtained along with on-target functionality evaluation results during online unit test. Furthermore, a cost-effective framework for online unit test is proposed. Because the runtime environment layer and the standard calibration environment are utilized to implement test interface, additional resource consumption of the target processor is minimized. Using the proposed development process model and unit test framework, the MOETs of 86 runnables for diesel EMS are obtained with 213 unit test cases. Using the obtained MOETs of runnables, the WCETs of tasks are estimated and the schedulability is evaluated. From the schedulability analysis results, the problems of the initially designed schedule table is recognized and it is fixed by redesigning of the runnable mapping and task offset. Through the various test scenarios, the proposed method is validated.

A Dynamic Voltage Scaling Algorithm for Dynamic Workloads

Dynamic Voltage Scaling (DVS) is a promising method to achieve energy saving by slowing down the processor into multiple frequency levels in battery-operated embedded systems. However, the worst case execution time (WCET) of the tasks scheduled by DVS must be known ahead of time to ensure their schedulability. In reality, a system's workloads may change significantly without satisfying any prediction. In other words, a task's WCET may not provide useful information about its future real execution time (RET). This paper presents a novel Dynamic-Mode EDF scheduling algorithm when workloads change significantly. One of the Single-Mode, Dual-Mode, and Three-Mode frequency setting formats can be applied, based on the RET and the accumulated slack at run-time. Only one combination of the number of modes/speeds, speed-switching transition points, and the frequency scaling factor for each mode can lead to the best energy saving. Experimental results show that, given an RET pattern, our Dynamic-Mode DVS algorithm achieves an average 15% energy savings over the traditional two-mode DVS scheme on hard real-time systems. Additionally, we also consider speed-switching or energy transition overhead, and implement a preliminary test of our proposed algorithm. With a less aggressive voltage scaling strategy (fewer speed changes for each job), deadlines can still be strictly satisfied and an average of 14% energy consumption saving over a non-DVS scheme is observed.

Parametric Timing Analysis

Embedded systems often have real-time constraints. Traditional timing analysis statically determines the maximum execution time of a task or a program in a real-time system. These systems typically depend on the worst-case execution time of tasks in order to make static scheduling decisions so that tasks can meet their deadlines. Static determination of worst-case execution times imposes numerous restrictions on real-time programs, which include that the maximum number of iterations of each loop must be known statically. These restrictions can significantly limit the class of programs that would be suitable for a real-time embedded system. This paper describes work-in-progress that uses static timing analysis to aid in making dynamic scheduling decisions. For instance, different algorithms with varying levels of accuracy may be selected based on the algorithm's predicted worst-case execution time and the time allotted for the task. We represent the worst-case execution time of a function or a loop as a formula, where the unknown values affecting the execution time are parameterized. This parametric timing analysis produces formulas that can then be quickly evaluated at run-time so dynamic scheduling decisions can be made with little overhead. Benefits of this work include expanding the class of applications that can be used in a real-time system, improving the accuracy of dynamic scheduling decisions, and more effective utilization of system resources.

An accurate worst case timing analysis for RISC processors

An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing effects of RISC's pipelined execution and cache memory, we propose extensions to the original timing schema where the timing information associated with each program construct is a simple time bound. In our approach, associated with each program construct is worst case timing abstraction, (WCTA), which contains detailed timing information of every execution path that might be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning operations on WCTAs are newly defined to replace the add and max operations on time bounds in the original timing schema. Our revised timing schema accurately accounts for the timing effects of pipelined execution and cache memory not only within but also across program constructs. The paper also reports on preliminary results of WCET analysis for a RISC processor. Our results show that tight WCET bounds (within a maximum of about 30% overestimation) can be obtained by using the revised timing schema approach. >