Tap FIR Filter Research Articles

Novel ASIC Design Flow Using Dynamic Libraries for Reducing Design Time

This paper presents an Electronic Design Automation (EDA) methodology, capable of complete ASIC design flow. It reduces the Non-Recurring Engineering (NRE) Cost by introducing a novel concept of dynamic technology library (DTL), which stores the layout and physical design information of each block in a design. DTLs are dynamically updated with a verified physical block, whenever a new design (not available in DTL) is synthesized. The key feature of DTL is that it offers reusability of verified physical blocks at different levels of abstraction (registers, functional units, gates etc.) thereby reducing the NRE cost. A depth based search technique is employed that allows partial or full reuse of pre-compiled and optimized design layouts. The proposed tool flow is validated using 16 designs from IWLS2005 benchmark suite, including one 32-bit ALU and a 15 tap FIR filter (widely used as a signal processing element). It is shown that the reusability offered by DTL makes it possible to reduce the design time by more than 90% in comparison to other EDA methodologies.

Design of High Performance Modified Wave pipelined DAA Filter with Critical Path Approach

In this paper, a new high speed control circuit is proposed which will act as a critical path for the data which will go from input to output to improve the performance of wave pipelining circuits The wave pipelining is a method of high performance circuit designs which implements pipelining in logic without the use of intermediate registers. Wave pipelining has been widely used in the past few years with a great deal of significant features in technology and applications. It has the ability to improve speed, efficiency, economy in every aspect which it presents. Wave pipelining is being used in wide range of applications like digital filters, network routers, multipliers, fast convolvers, MODEMs, image processing, control systems, radars and many others. In previous work, the operating speed of the wave-pipelined circuit can be increased by the following three tasks: adjustment of the clock period, clock skew and equalization of path delays. The path-delay equalization task can be done theoretically, but the real challenge is to accomplish it in the presence of various different delays. So, the main objective of this paper is to solve the path delay equalization problem by inserting the control circuit in wave pipelined based circuit which will act as critical path for the data that moves from input to output. The proposed technique is evaluated for DSP applications by designing 4- tap FIR filter using Distributed arithmetic algorithm (DAA). Then comparison of this design is done with 4-tap FIR filter designs using conventional pipelining and non pipelining. The synthesis and simulation results based on Xilinx ISE Navigator 12.3 shows that wave pipelined DAA based filter is faster by a factor of 1.43 compared to non pipelined one and the conventional pipelined filter is faster than non pipelined by factor of 1.61 but at the cost of increased logic utilization by 200 %. So, the wave-pipelined DA filters designed with the proposed control circuit can operate at higher frequency than that of non-pipelined but less than that of pipelined. The gain in speed in pipelined compared to that of wavepipelined is at the cost of increased area and more dissipated power. When latency is considered, wavepipelined design filters with the proposed scheme are having the lowest latency among three schemes designed.

Design and implementation of an Asynchronous Controller for FPGA Based Asynchronous Systems

In a clause of combinational circuits, the throughput can be increased, without (wave) pipelining, by introducing data dependent delay feature thus avoiding the worst case delay. That is, in circuits like multipliers and adders which are the basic building blocks of any DSP system; the processing delay can be varied according to the magnitude of the input data. This makes the circuit asynchronous and necessitates a controller to arbitrate the data. Systems like FIR filters, where a series of combinational multipliers are used, can be asynchronously pipelined with a controller regulating the data between stages. With this system level pipelining, speed of circuit level pipelining can be achieved provided the data are of low magnitude. In this paper, two controller architectures are presented to regulate the data flow between asynchronously pipelined stages. Firstly, as a stepping stone, Altera‟s soft-core NIOS processor [1] is used and secondly, an exclusive asynchronous controller is designed using HDL. These controllers are designed to suit asynchronous implementation in conventional FPGAs, to effectively handle repeated data and to perform self-test. These controllers issue the control signals to the various dual edge triggered pipelined registers to process the data in both the edges for further improving speed. In the HDL version of the controller, programmable delays are generated by a „logic locked‟ high frequency counter without using delay elements. To verify the efficacy of these controllers 2 tap FIR filter is implemented using Braun array multipliers and adders. Thus, this approach consumes lower power and achieves data dependent throughput and also avoids the need for global clock signals and skew problems.

The Chameleon Architecture for Streaming DSP Applications

We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8mm2 in a 130nm process), is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool.

Study of transverse bunch-by-bunch feedback systems based on the two tap FIR filter

A signal-processing system based on two-tap digital filters has been systematically studied considering its application to bunch feedback systems. Through studies we have found that the two-tap-filter-based system is a hopeful candidate for the signal processor used in high-speed, large-scale bunch feedback systems.

FIR filters with field-programmable gate arrays

Distributed arithmetic techniques are the key to efficient implementation of DSP algorithms in FPGAs. The distributed arithmetic process is briefly described. A representative DSP design application in the form of an 8 tap FIR filter is offered for the Xilinx XC3042 field programmable logic array (FPGA). The design is presented in sufficient detail--from filter specifications via filter design software through detailed logic of salient data and control functions to obtain a realistic placing and routing of configurable logic block (CLBs) and in/out block (IOBs) components for simulation verification and performance evaluation vis-a-vis commercially available dedicated 8 tap FIR filter chips.