Tap Finite Impulse Response Filter Research Articles

RDO-WT: optimised Wallace Tree multiplier based FIR filter for signal processing applications

ABSTRACT Digital Signal Processing (DSP) and communication applications utilise a Finite Impulse Response (FIR) filter which is key component for digital communication. Moreover, quality of signal is enhanced by FIR filter which is mostly employed by filtering applications. The execution speed of the FIR is determined by multiplier’s performance. Hardware resource utilisation and speed-up operations are some of the issues found in existing methods which are occurred due to a critical path in incomplete products. So, this can be improved by the proposed optimisation algorithm based multiplier. This research establishes the execution of FIR Filter design using Red Deer Optimisation (RDO) based Wallace Tree (WT) multiplier. By using the optimised WT multiplier, FIR filter is simulated to examine the area, delay, power and frequency for different tap FIR filter. Moreover, FIR filter with optimised WT is introduced to perform signal denoising application. Proposed multiplier design is simulated using Xilinx tool. Filtering simulation is done by using the publicly available database named as MIT-BIH database and the noise removal process is simulated using Matlab tool. The FIR filter designed with proposed multiplier provides delay around 1.373 ns and consumes 0.143 W as total power which is lesser than the existing methods.

Heterogeneous Adder Based FIR Filter Design And Simulation

The finite impulse response (FIR) is one of the important filters in digital signal processing (DSP) as it responds for a finite duration and settles to zero on the finite time. Digital FIR filters are programmable in nature and its behavior can be understood with the help of the program and can be easily programmed for the memory of a processor. The digital filters can be replaced without change of the hardware or the external circuitry. The 7 tap FIR filter needs 16 numbers of multipliers and 9 adders which are used in parallel form. The paper focused on the chip design and implementation of the FIR filter with a decimal adder and heterogeneous adder is done using VHDL programming in Xilinx 14.2 ISE software and the same is synthesized on SPARTAN - 3E FPGA to verify the results. Moreover, the functional simulation is done in Modelsim 10.0 software. Hardware utilization parameters, combinational path delay, memory utilization parameters are directly extracted from the Xilinx software for FIR filter architecture based on decimal adder and heterogeneous adders. The comparative analysis of the FIR filter is done with heterogeneous adder architecture lead an area and delay efficient design for DSP applications

Design and Implementation of Hybrid FIR Filters using Vedic Multiplier and Fast Adders

FIR (Finite Impulse Response) filters play a significant role in the field of Digital Signal Processing (DSP) to eliminate noise suppression in Electro Cardio Graph (ECG), Imaging devices and the signal stored in analog media. So filter evaluation is accomplished to reduce the noise level. The Filter passes only the desired frequency to pass thereby reducing distortion in the processed signal during measurement. The FIR filter comprises of basic units like adders, multipliers and the delay element for its operations.FIR and IIR are the two types of digital filters chosen based on the range of inputs, complexity and size requirement. Multipliers and adders play a vital role in deterring the performance of FIR filter. In this work, we design and analyze different multiplier and adder for high-performance Fir filter implementation. The Vedic Mathematics is the methods containing 16 Sutras to aid fast mental calculations. In this work, we propose modified Anurupye Vedic multiplier methods with Kogge Stone fast adder for implementation in the direct form FIR filter. This approach provides 1.5% decrease in delay and 10.2% reduced in power, hence increasing speed marginally than previous methods. Along with low power consumption in Very High-Speed Hardware Description Language (VHDL), all the adders and the multiplier topologies are Synthesized using (Xilinx Spartan – 6 FPGA) Trainer Kit and the proposed 8 – Tap FIR filter is executed using this Board.

Reliability improved, high performance FIR filter design using new computation sharing multiplier: suitable for signal processing applications

The finite impulse response (FIR) filter are class of digital filter are extensively used in signal processing and in communication system applications such as noise reduction, echo cancellation and image enhancement etc. Designing a FIR filter with less computation time, low power and by using minimum hardware playing a major role in overall performance of the application where FIR filter is involved. The research work presented in this paper has been carried out to fulfil the above said aim. In this research work, 16 tap FIR filter has been implemented using newly proposed floating point Computation Sharing High Speed Multiplier (CSHM). Since in FIR filter, floating point multiplication is involved in each and every tap of filter operation, bringing the floating point multiplication architecture with less computation time, low power and with minimum hardware will automatically improve the performance of FIR filter. The newly proposed computation sharing multiplier differs from existing computation sharing multiplier with respect to fixed alphabet entries in a precomputer unit and efficient computation of distributed arithmetic based vector scalar product. Front end and backend design of a 16 tap FIR filter using newly proposed CSHM and existing CSHM has been carried out using Cadence® nclaunch®, RC® and Encounter® tool with tsmc 180 nm technology library. Comparison result of 16 tap FIR filter shows that 18% reduction in chip power, 13% reduction in chip area and 26% reduction in cell count has been achieved with newly proposed floating point CSHM compare to 16 tap FIR filter designed with existing CHSM. This research work also proposes efficient automation algorithms which improve the design for manufacturability (DFM) of a post layout of a 16 tap FIR filter designed which will improve the reliability of integrated circuits. There are many DFM guidelines have to be followed during layout design. In this research work, the automation algorithm has been proposed for one of the DFM guideline called VIA-Redundancy. The aim of this automation algorithm is to replacing single VIA with double VIA wherever possible. In case of “L” transition routing, single contacts can be very sensitive to resistivity spread and defect. The probability to have too resistive transition will be very much minimized by inserting a new contact which reduces electro-migration effect. Through this automation algorithm redundancy percentage of all the VIA’s of FIR filter designed has been increased without compromising chip area, power and computation time much. The specialty of this automated algorithm is that this can be used to any design which has been implemented on the same platform and technology node. The proposed algorithm automated through Tcl 8.6, UNIX platform.

Analysis and Implementation of High Performance Reconfigurable Finite Impulse Response Filter Using Distributed Arithmetic

The finite impulse response (FIR) digital filters are commonly used in many digital signal processing systems. For higher order filters the implementation of reconfigurable random access memory based FIR filter becomes costly and the speed is reduced. This research paper presents an efficient distributed arithmetic (DA) based approach for reduced area and low power implementation of the FIR filters whose filter coefficients are dynamic in nature. Due to the complexity in implementation of higher order filters, a portion of bit serial based computation in the look up table (LUT) is used. However the shared LUTs are used instead of RAM based LUTs, Shared LUTs involves the concept of LUT partitioning where the coefficients are split into vectors of smaller bit lengths which reduce the depth of the LUT. The possible partial DA results for these vectors are stored in register banks that are shared between multiple DA units. Since the register banks are shared, the area is effectively reduced. Hence an application specific integrated circuits implementation is used. When compared to the existing 256 tap FIR filter, the area has been reduced by 62.16% for vector bit length (M), M = 2 and by 75.84% for M = 4 and the power consumption has been reduced by 42.67% for M = 2 and by 64.02% for M = 4.

Reliable Low Power FIR Filter using Vedic Multiplier

Recent trends in mobile computing and multimedia application demand low power digital signal processing systems (DSP). The most important block in any DSP system is a finite impulse response (FIR) filter. Here a reliable low power FIR filter is designed using Vedic multipliers which specifically perform addition and shifting operation. The addition is done using full adder with 9 transistors which use only 3 transistor XOR gate. A four tap FIR filter was implemented in microwind 2 electronic design automation tool using CMOS 90nm technology. In the proposed design the power consumption is reduced by 23% and delay has been reduced by 44% when compared with the existing FIR filters.

Realization of Low Power FIR Digital Filter using Modified DA-based Architecture

Objectives: Finite Impulse Response (FIR) filters are widely used in image and signal processing applications and responsible for more total power dissipation. This research work presents modified Distributed Arithmetic (DA)-based approach for realization of low power FIR digital filter. Methods/Statistical Analysis: Power reduction in modified DA-based filter is achieved by turning off the MOS components whenever the input samples of circuit are zero. The proposed filter reduces power consumption by disabling adder operation when inputs are zero. In the conventional DSP applications, it is observed that the average of the zero input sample is very high. Therefore, substantial reduction in power consumption can be obtained by proposed modified DA-based architecture. The proposed DA-based FIR filter is designed using Xilinx® ISE design tool and Cadence® EDA tool. Findings: The proposed work proved that the power reduction is achieved in modified DA-based FIR filter realization when compared with existing LUT-less DA-based architecture of FIR filter. Simulation results shows that proposed architecture can achieve significant power reduction with fewer percentage increases in area and delay for different architectures. For four tap FIR filter 12.5% power reduction is achieved, at the cost of 0.63% extra chip area and 1% increased delay in comparison with conventional DA-based filter architecture. Therefore, the proposed filter can achieve even greater power saving for higher order FIR filters and for more number of zeros in the inputs sample. The proposed technique can also be used for reconfigurable architectures where filter coefficients change during runtime. Conclusion: A low power modified DA-based FIR digital Filter is proposed. Power reduction in proposed design is due to turning off MOS components and is linearly related to number of zeros in input and order of the filter.

Multiplierless FIR Filter Implementation on FPGA

Area complexity in the algorithm of finite impulse response (FIR) filter is mainly caused by multipliers. Among the multiplierless techniques of FIR filter, Distributed Arithmetic is most preferred area efficient technique. In this technique, precomputed values of inner product are stored in LUT, which are further added and shifted with number of iterations equal to the precision of input samples. But the exponential growth of LUT with the order of FIR filter, in its basic structure, makes it prohibitive for many applications. An improvement over the basic DA structure is presented in this paper, by the use of slicing of LUT to the desired length. An architecture of 16 tap FIR filter is presented, with different length of slice of LUT. Design implementation and synthesis result shown the improvement in speed of operation as well as saving in area, with more number of slices. Found drastic improvement in speed, when compared with earlier result.

Recursive architecture using pipeline stall for low complexity MPEG-4 ALS encoder

An MPEG-4 audio lossless coding (ALS) encoder consists of a short-term predictor, a joint coder, a long-term predictor, and an entropy coder for audio signal compression. Especially, the short-term predictor is the highest complexity in MPEG-4 ALS encoder implementation because linear prediction coefficients (LPCs) for the short-term predictor are obtained from the Levinson-Durbin recursion algorithm that uses correlations of the input signals. LPCs are used for the finite impulse response (FIR) filter of the short-term predictor and its maximum coefficient order is up to 1023. Proposed is an area-efficient short-term predictor through the recursive architecture using pipeline stall and the modified radix-2 FIR algorithm is proposed. The proposed shot-term predictor has a reduction of complexity by about 95% compared to the radix-2 1024 tap FIR filter.