Systolic Structure Research Articles

High-performance unified modular multiplication algorithm and hardware architecture over G(2m)

The finite field Modular Multiplier (MM) over GF (2m) based on the National Institute of Standards and Technology (NIST) recommended polynomials can be used as a critical component in many cryptosystems. But much of the research suffers from the problems of only supporting a single curve or being very inefficient. In this paper, we present a KA-based unified algorithm (hybrid field size) and its corresponding architecture for high-performance implementation of the systolic modular multiplier over GF (2m), which can support all the NIST recommended polynomials. A number of efficient techniques have been explored and used to realize a high-performance implementation of the multiplier. First, we propose a three-term KA based MM approach and make it fit for systolic implementation. Second, we propose a configurable, unified irreducible polynomial that can support all five curves recommended by NIST and the corresponding modular reduction method. Third, the corresponding systolic structure is also designed in accordance with (1) and (2) to improve efficiency, and we adopt register sharing and computation unit sharing methods to reduce the space complexity of the proposed structure. Additionally, parallel computation of two163-width MMs is employed to improve resource utilization further. From the synthesis results on ASIC, it is shown that the proposed multipliers have significantly lower latency and higher performance than the existing designs. e.g., the proposed structure could achieve up to a 73 % reduction in area-delay product (ADP) over the existing structures.

A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing

There is an emerging need to design multi-precision floating-point (FP) accelerators for high-performance-computing (HPC) applications. The commonly-used methods are based on high-precision-split (HPS) and low-precision-combination (LPC) structures, which suffer from low hardware utilization ratio and various multiple clock-cycle processing periods. In this brief, a new multi-precision FP processing element (PE) is developed with proposed bit-partitioning method. Minimized redundant bits and operands are achieved. The proposed PE supports <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16\times $ </tex-math></inline-formula> half-precision (FP16), <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula> single-precision (FP32) and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1\times $ </tex-math></inline-formula> double-precision (FP64) operations with 100% multiplication hardware utilization ratio. Besides, vector systolic structure is designed for PE array to increase the system-level throughput and energy efficiency. The proposed design is realized in a 28-nm process with 1.351-GHz clock frequency. Compared with the existing multi-precision FP methods, the proposed work exhibits the best energy-efficiency performance of 1193 GFLOPS/W at FP16, 317 GFLOPS/W at FP32 and 77.3 GFLOPS/W at FP64 with at least 22.3%, 30% and 3.3% improvement, respectively.

Field programmable gate array implementation of an adaptive filtering based noise reduction and enhanced compression technique for healthcare applications

AbstractNowadays, the development of e‐health monitoring devices is getting more demand for remote health applications. In addition, cardiovascular diseases is considered the most chronic disease in recent years. So, this requires a fast diagnosis and therapy to clear this issue and requires an information transformation from the patient to the distant hospital. But, it faces many challenges like more energy consumption, data security, storage, and transmission. In addition, the electrocardiogram (ECG) data must be processed in real‐time, and the information must have high predictability and lossless compression. So, in this article, an enhanced set partitioning in hierarchical tree decoder with deep belief neural network is developed for ECG compression. Due to an inappropriate channel in telemedicine applications, the ECG signals transmitted through a wireless network are affected by noise. So, fast normalized least mean square (FNLMS) algorithm based adaptive filter is deliberated to eliminate the unwanted noise from the ECG signal. Also, the structure of the FNLMs based adaptive filter is modified by developing a systolic structure to increase the speed of filtering process. Moreover, the parallel and pipelined architecture is provided for the proposed compression unit to reduce the processing time and the area overhead as compared to the existing methods. A publicly available database called the MIT‐BIH database and real‐time ECG data records are used for simulation purposes. The proposed design was implemented on the Xilinx platform and the MATLAB tool. The performance of the proposed design is estimated by the parameters like compression ratio, signal to noise ratio, root mean square error, and percentage root mean square difference (PRD), PRD normalized, and quality‐score. It is compared with existing designs to show the efficiency of our proposed design.

A Low-Power Area-Efficient Precision Scalable Multiplier with an Input Vector Systolic Structure

In this paper, a small-area low-power 64-bit integer multiplier is presented, which is suitable for portable devices or wireless applications. To save the area cost and power consumption, an input vector systolic (IVS) structure is proposed based on four 16-bit radix-8 Booth multipliers and a data input scheme is proposed to reduce the number of signal transitions. This structure is similar to a systolic array in matrix multiply units of a Convolutional Neural Network (CNN), but it reduces the number of processing elements by 3/4 concerning the same vector systolic accelerator in reference. The comparison results prove that the IVS multiplier reduces at least 61.9% of the area and 45.18% of the power over its counterparts. To increase the hardware resource utilization, a Transverse Carry Array (TCA) structure for Partial Products Accumulation (PPA) was designed by replacing the 32-bit adders with 3/17-bit adders in the 16-bit multipliers. The experiment results show that the optimization could lead to at least a 6.32% and 13.65% reduction in power consumption and area cost, respectively, compared to the standard 16-bit radix-8 Booth multiplier. In the end, the precise scale of the proposed IVS multiplier is discussed. Benefiting from the modular design, the IVS multiplier can be configured to support sixteen different kinds of multiplications at a step of 16 bits [16b, 32b, 48b, 64b] × [16b, 32b, 48b, 64b].

Proposal of Smith-Waterman algorithm on FPGA to accelerate the forward and backtracking steps.

In bioinformatics, alignment is an essential technique for finding similarities between biological sequences. Usually, the alignment is performed with the Smith-Waterman (SW) algorithm, a well-known sequence alignment technique of high-level precision based on dynamic programming. However, given the massive data volume in biological databases and their continuous exponential increase, high-speed data processing is necessary. Therefore, this work proposes a parallel hardware design for the SW algorithm with a systolic array structure to accelerate the forward and backtracking steps. For this purpose, the architecture calculates and stores the paths in the forward stage for pre-organizing the alignment, which reduces the complexity of the backtracking stage. The backtracking starts from the maximum score position in the matrix and generates the optimal SW sequence alignment path. The architecture was validated on Field-Programmable Gate Array (FPGA), and synthesis analyses have shown that the proposed design reaches up to 79.5 Giga Cell Updates per Second (GCPUS).

Low-Space Bit-Parallel Systolic Structure for AOP-Based Multiplier Suitable for Resource-Constrained IoT Edge Devices

Security and privacy issues with IoT edge devices hinder the application of IoT technology in many applications. Applying cryptographic protocols to edge devices is the perfect solution to security issues. Implementing these protocols on edge devices represents a significant challenge due to their limited resources. Finite-field multiplication is the core operation for most cryptographic protocols, and its efficient implementation has a remarkable impact on their performance. This article offers an efficient low-area and low-power one-dimensional bit-parallel systolic implementation for field multiplication in GF(2n) based on an irreducible all-one polynomial (AOP). We represented the adopted multiplication algorithm in the bit-level form to be able to extract its dependency graph (DG). We choose to apply specific scheduling and projection vectors to the DG to extract the bit-parallel systolic multiplier structure. In contrast with most of the previously published parallel structures, the proposed one has an area complexity of the order O(n) compared to the area complexity of the order of O(n2) for most parallel multiplier structures. The complexity analysis of the proposed multiplier structure shows that it exhibits a meaningful reduction in area compared to most of the compared parallel multipliers. To confirm the results of the complexity analysis, we performed an ASIC implementation of the proposed and the existing efficient multiplier structures using an ASIC CMOS library. The obtained ASIC synthesis report shows that the proposed multiplier structure displays significant savings in terms of its area, power consumption, area-delay product (ADP), and power-delay product (PDP). It offers average savings in space of nearly 33.7%, average savings in power consumption of 39.3%, average savings in ADP of 24.8%, and savings in PDP of 31.2% compared to the competitive existing multiplier structures. The achieved results make the proposed multiplier structure more suitable for utilization in resource-constrained devices such as IoT edge devices, smart cards, and other compact embedded devices.

Low-latency area-efficient systolic bit-parallel GF(2[formula omitted]) multiplier for a narrow class of trinomials

Edge computing in Internet of Things (IoT) requires high-performance as well as cost-effective hardware implementations to accommodate large number of computations. Implementation of security in IoT edge devices is indispensable, and attaining security is possible using Elliptic curve cryptography (ECC) algorithms. Finite field GF(2m) multiplication is a performance-critical operation in these algorithms, hence, it requires efficient hardware implementations. Systolic structures for GF(2m) multiplier are suitable for high-performance applications as they allow high-throughput implementations. Many systolic GF(2m) multipliers have been proposed in the literature that can achieve high throughput rates, however, they require large area and high latency. In this paper, we propose a polynomial basis GF(2m) systolic multiplier applicable for a narrow class of trinomials which includes both the NIST (National Institute of Standards and Technology) recommended trinomials for m=233 and 409 fields. Analytical comparisons with the related multipliers for m=409 show that the multiplier proposed in this paper reduces the latency by 32% and area by 5%. The proposed multiplier is synthesized using synopsis tools targeting for an ASIC implementation and the comparisons are also presented. The proposed low-latency area-efficient multiplier can be used in the implementation of hardware security for low-cost IoT edge devices.

High-throughput area-delay-efficient systolic multiplier over GF(2m) for a class of trinomials

The paradigm of Edge Computing in Internet of Things (IoT) demands high-throughput implementations of IoT edge devices. Security algorithms used in these devices heavily use GF(2m) multiplications. Systolic structures for GF(2m) multipliers can offer high throughput rates along with other features such as regularity, concurrency, and modularity. Many systolic architectures for GF(2m) multiplier were proposed in the literature to achieve low area and time complexities. In this paper, we propose a high-throughput and low area-delay complexity systolic structure for the hardware realization of polynomial basis multiplication in GF(2m) for a class of trinomials. The complexity analysis shows that the proposed architecture results in achieving high throughput and less area-delay complexity compared with the existing polynomial basis multipliers in the literature. When compared with the best available multipliers, the multiplier realized using the proposed architecture achieves throughput improvement by 42% and reduction in area-delay product by 7% for m=409. Application specific integrated circuit (ASIC) implementations of the proposed multiplier and the best available multipliers confirm that the proposed multiplier outperforms the other multipliers. Hence, the proposed high-throughput area-delay-efficient multiplier can be employed in IoT edge devices.

A Secure Architecture for Modular Division over a Prime Field against Fault Injection Attacks

Fault injection attacks pose a serious threat to many cryptographic devices. The security of most cryptographic devices hinges on a key block called modular division (MD) over a prime field. Although a lot of research has been done to implement the MD over a prime field in hardware efficiently, studies on secure architecture against fault injection attack are very few. A few of the studies that focused on secure architecture against fault injection attack can only detect faults but not locate faults. In this regard, this paper designs a novel secure architecture for the MD over a prime field, which can not only detect faults, but also can locate the error processing element. In order to seek the best optimal performance, four word-oriented systolic structures of a main function module (MFM) were designed, and three error detection schemes were developed based on different linear arithmetic codes (LACs). The MFM structures were combined flexibly with the error detection schemes. The time and area overheads of our architecture were analyzed through the implementation in an application-specific integrated circuit (ASIC), while the error detection and location capabilities of our architecture were demonstrated by C++ simulation, in comparison to two existing methods. The results show that our architecture can detect single-bit error (SBE) with 100% accuracy and locate the erroneous processing element (PE), and correctly identify most of the single PE errors and almost all of the multi-PE errors (when there are more than three erroneous PEs). The only weakness of our architecture is the relatively high time and area overhead ratios.

The Algorithm and Structure for Digital Normalized Cross-Correlation by Using First-Order Moment.

Normalized cross-correlation is an important mathematical tool in digital signal processing. This paper presents a new algorithm and its systolic structure for digital normalized cross-correlation, based on the statistical characteristic of inner-product. We first introduce a relationship between the inner-product in cross-correlation and a first-order moment. Then digital normalized cross-correlation is transformed into a new calculation formula that mainly includes a first-order moment. Finally, by using a fast algorithm for first-order moment, we can compute the first-order moment in this new formula rapidly, and thus develop a fast algorithm for normalized cross-correlation, which contributes to that arbitrary-length digital normalized cross-correlation being performed by a simple procedure and less multiplications. Furthermore, as the algorithm for the first-order moment can be implemented by systolic structure, we design a systolic array for normalized cross-correlation with a seldom multiplier, in order for its fast hardware implementation. The proposed algorithm and systolic array are also improved for reducing their addition complexity. The comparisons with some algorithms and structures have shown the performance of the proposed method.

A novel implementation of combined systolic and folded architectures for adaptive filters in FPGA

The adaptive filter constitutes an important part of statistical signal processing. Adaptive filters are often realized either as a set of program instructions running on an arithmetical processing device such as a Microprocessor or Digital Signal Processing (DSP) chip, or as a set of logic operations implemented in a field programmable gate array (FPGA) or in Very Large Scale Integrated Circuit (VLSI). Systolic architecture improves the speed of the system at the cost of increased area. On the other hand, folding technique uses less hardware resources. A combination of systolic and folding structures provides improvement in speed and reduction in area. This paper presents a novel idea of combining Systolic and Folding architectures and its design in various adaptive filters like Recursive Least Square (RLS), Affine Projection (AP) and Kalman filters. The structures are designed using Xilinx System Generator tool of MATlab 2015 and implemented in Xilinx Virtex 5 FPGA. The designed structures are tested for noise cancellation in Electrocardiogram (ECG) signal and results are analysed for various order of all the filters and its metrics are analysed in terms of Signal to Noise Ratio(SNR), Mean Square Error(MSE), area and speed. From the analysis it is observed that the proposed folding in systolic structures improves SNR by 6.77% in RLS, 4.68% in Affine projection and 2.13% in Kalman Algorithm than the conventional structures. It is inferred that the proposed design in Affine projection shows improved SNR than the other filters. The proposed combined folding in systolic architecture shows 18.35% reduction in area and reduction in delay.

Decimator systolic arrays design space exploration for multirate signal processing applications

This study presents a new systolic array structure for a decimator that merges the antialiasing finite impulse response (FIR) filter with the downsampler. The development of the structure is based on a systematic methodology. Using this methodology, a dependence graph for the decimator was obtained that combined the antialiasing filter and the downsampler. Different data scheduling and projection operations were developed to obtain different proposed designs. Six systolic array design options were obtained and evaluated. The fastest design was selected for hardware implementation and compared with the other two well known decimator designs; namely, conventional design, in which the antialiasing filter is followed by a downsampling and the polyphase design, in which a commutator is followed by the polyphase antialiasing filter. Field-programmable gate array implementations for the proposed and the other two designs confirm that the proposed decimator implementation outperforms in terms of area, speed, and power as the decimation factor increases regardless of the number of FIR filter coefficients.

Novel Pipelined Scalable Systolic Multiplier Based on Irreducible All-One Polynomials

A planned productive structure issued for the systolic execution of authoritative based limited field duplication over G F(2 m) in light of final 56-bit AOP is proposed in this work. We extricated a recursive increase calculation and utilized it to plan an intermittent and confined piece level reliance outline (DG) for systolic registering. The intermittent piece level DG is changed into a very smal grained DG, and the pipe coating is utilized for snappier mapping into a parallel systolic design. It doesn't require any overall correspondences for measured decline, in contrast to most current developments. The suggested bit-parallel systolic structure is similar to the parallel systolic structure, however the quantity of registers is altogether lower.

Calculation of data processing time for an acyclic wavefront array processor

The wavefront array processor is a systolic structure that implements the principle of data flow control. The paper is devoted to methods for calculating the performance of an acyclic wavefront array processor. Data processing is gradient if at each moment of time all operations for which their input data are ready should be performed. It has been established that gradient processing has minimal time. A graph with weighted vertices is constructed, the maximum path length is equal to the processing time of a given amount of data for an acyclic wavefront array processor. An algorithm for the calculation the processing time of a given amount of data by this processor is proposed. The results can be used to calculate performance in the development of processors, co-processors, multi-threaded cloud applications implementing business processes, as well as non-linear pipelines associated with mass production.

Knowledge-based single-tone digital filter implementation for DSP systems

The requirement for efficient digital signal processing (DSP) systems and its solutions increases highly over the last few years. DSP techniques as well as its algorithms are necessary for day to day life tool namely smartphone, set-top unit (STU), video and acoustic players, digital cameras, digital television, etc. This paper describes a comparative study on knowledge-based digital filter structure namely transposed form, direct form, and systolic array. To implement the parallel processing the systolic array structure is often used. A Goertzel algorithm is implemented in the field-programmable gate array (FPGA) Altera EP4CE115F29C7 device which is used to determine the discrete Fourier transform (DFT). Finally, filtering technique is implemented efficiently by dividing filter coefficients and data into odd and even which increases the computational speed. The computational speed and functional verification results are achieved by using MATLAB. The Altera DSP builder and Simulink are used for the implementation of Goertzel algorithm. The 64-tap systolic low-pass filter structures offer 213.97-μs-less delay than the transposed form, 1700 μs, and direct form, 3900 μs, structures. Similarly for 2048-tap low-pass filter using sub-filter offers 49.397-ms computational speed and direct filtering offers 53.257 ms.

Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix–Vector Product Approach

Systolic finite field multiplier over $GF(2^{m})$ , because of its superior features such as high throughput and regularity, is highly desirable for many demanding cryptosystems. On the other side, however, obtaining high-performance systolic multiplier with relatively low hardware cost is still a challenging task due to the fact that the systolic structure usually involves large area complexity. Based on this consideration, in this paper, we propose to carry out two novel coherent interdependent efforts. First, a new digit-serial multiplication algorithm based on polynomial basis over binary field $(GF(2^{m}))$ is proposed. Novel Toeplitz matrix–vector product (TMVP)-based decomposition strategy is employed to derive an efficient subquadratic space complexity. Second, The proposed algorithm is then innovatively mapped into a low-complexity systolic multiplier, which involves less area-time complexities than the existing ones. A series of resource optimization techniques also has been applied on the multiplier which optimizes further the proposed design (it is the first report on digit-serial systolic multiplier based on TMVP approach covering all irreducible polynomials, to the best of our knowledge). The following complexity analysis and comparison confirm the efficiency of the proposed multiplier, that is, it has lower area-delay product (ADP) than the existing ones. The extension of the proposed multiplier for bit-parallel implementation is also considered in this paper.

New approach to low-area, low-latency memory-based systolic architecture for FIR filters

A new approach to memory based systolic architecture for higher order FIR filter has been proposed. The memory- based multiplier used in this systolic FIR filter design is different from the earlier used memory-based multipliers. This design is applicable for low-area, low latency and high throughput FIR filters. Both 1-D and 2-D systolic computing structures for higher order FIR filter are derived and implemented in Xillinx Virtex-7 XC7vx330tffg1157 FPGA using VHDL. Various performance metrics like number of slices, latency of the filter and maximum frequency of operation of the filter are compared for different filter orders at various input sample length. The parameters are compared for both 1-D and 2-D systolic structure. For a 128-order filter with an input length of 32-bit, the proposed 2-D structure at eighth-level decomposition occupies 88.9% less area as compared to 1-D structure. The latency of the filter is reduced from 127.5ns to 3.5ns for a 128-order filter using the proposed decomposed structure.

Low‐complexity unidirectional systolic Dickson basis multiplier for lightweight cryptosystems

Finite field multiplier is a very important operation for realising elliptic curve cryptography. Dickson basis is a recently developed basis for representing finite elements in GF(2 m ). This study will propose a unidirectional systolic multiplier for such Dickson basis. The unidirectional systolic structure offers low space and time complexities and can be easily modified to have error detection capability which can resist side-channel attacks.

Efficient Parallel and Serial Systolic Structures for Multiplication and Squaring Over GF(${2^{m}}$ )

Efficient Parallel and Serial Systolic Structures for Multiplication and Squaring Over GF(${2^{m}}$ )

Low Register-Complexity Systolic Digit-Serial Multiplier Over Based on Trinomials

Digit-serial systolic multipliers over $GF(2^m)$ based on the National Institute of Standards and Technology (NIST) recommended trinomials play a critical role in the real-time operations of cryptosystems. Systolic multipliers over $GF(2^m)$ involve a large number of registers of size $O(m^2)$ which results in significant increase in area complexity. In this paper, we propose a novel low register-complexity digit-serial trinomial-based finite field multiplier. The proposed architecture is derived through two novel coherent interdependent stages: (i) derivation of an efficient hardware-oriented algorithm based on a novel input-operand feeding scheme and (ii) appropriate design of novel low register-complexity systolic structure based on the proposed algorithm. The extension of the proposed design to Karatsuba algorithm (KA)-based structure is also presented. The proposed design is synthesized for FPGA implementation and it is shown that it (the design based on regular multiplication process) could achieve more than 12.1 percent saving in area-delay product and nearly 2.8 percent saving in power-delay product. To the best of the authors’ knowledge, the register-complexity of proposed structure is so far the least among the competing designs for trinomial based systolic multipliers (for the same type of multiplication algorithm).