Systolic Array System Research Articles

The Optimal Architecture Design of Two-Dimension Matrix Multiplication Jumping Systolic Array

This paper proposes an efficient systolic array construction method for optimal planar systolic design of the matrix multiplication. By connection network adjustment among systolic array processing element (PE), the input/output data are jumping in the systolic array for multiplication operation requirements. Various 2-D systolic array topologies, such as square topology and hexagonal topology, have been studied to construct appropriate systolic array configuration and realize high performance matrix multiplication. Based on traditional Kung-Leiserson systolic architecture, the proposed “Jumping Systolic Array (JSA)” algorithm can increase the matrix multiplication speed with less processing elements and few data registers attachment. New systolic arrays, such as square jumping array, redundant dummy latency jumping hexagonal array, and compact parallel flow jumping hexagonal array, are also proposed to improve the concurrent system operation efficiency. Experimental results prove that the JSA algorithm can realize fully concurrent operation and dominate other systolic architectures in the specific systolic array system characteristics, such as band width, matrix complexity, or expansion capability.

A concurrent system for the computation of higher-order moments

The cumulants defined in terms of moments are basic to the study of higher-order statistics (HOS) of a stationary stochastic process. This paper presents a concurrent systolic array system for the computation of higher-order moments. The system allows for the simultaneous computation of the second-, third-, and fourth-order moments. The architecture achieves good speedup through its excellent exploitation of parallelism, pipelining, and reusability of some intermediate results. The computational complexity and system performance issues related to the architecture are discussed. The concurrent system is designed with the CMOS VLSI technology and is capable of operating at 3.9 MHz.

Real-time phase-angle measurement

There are many techniques for phase-angle measurement. One technique is to use the least squares method (LSM). However, this method involves huge computations, especially when the number of samples is large. This paper presents an efficient systolic array system to speed up the LSM computation in a parallel and pipeline manner. The computation time, the speedup of the system and the delay of the processing elements (PEs) are all evaluated. The internal structure of the PEs is also described. The system is shown to be almost eight times faster than a uniprocessor system. The system is amenable for VLSI implementation.

A generic systolic array building block for neural networks with on-chip learning

Neural networks require VLSI implementations for on-board systems. Size and real-time considerations show that on-chip learning is necessary for a large range of applications. A flexible digital design is preferred here to more compact analog or optical realizations. As opposed to many current implementations, the two-dimensional systolic array system presented is an attempt to define a novel computer architecture inspired by neurobiology. It is composed of generic building blocks for basic operations rather than predefined neural models. A full custom VLSI design of a first prototype has demonstrated the efficacy of this design. A complete board dedicated to Hopfield's model has been designed using these building blocks. Beyond the very specific application presented, the underlying principles can be used for designing efficient hardware for most neural network models.

A bit-level systolic architecture for implementing a VQ tree search

A bit-level systolic array system for performing a binary tree Vector Quantization codebook search is described. This consists of a linear chain of regular VLSI building blocks and exhibits data rates suitable for a wide range of real-time applications. A technique is described which reduces the computation required at each node in the binary tree to that of a single inner product operation. This method applies to all the common distortion measures (including the Euclidean distance, the Weighted Euclidean distance and the Itakura-Saito distortion measure) and significantly reduces the hardware required to implement the tree search system.

Design of one-dimensional systolic-array systems for linear state equations

To solve linear state equations, a two-dimensional systolic-array system has been proposed. For the same purpose, various kinds of one-dimensional arrays have been designed and discussed by the authors. The linear systolic-array system with first-in-first-out (FIFO) queues can be designed by applying double projections from the three-dimensional dependence graph (DG). As the array thus designed needs processors with multifunction operations and various input/output requirements, tag control bits are incorporated, and so make the overall computation more efficient. Furthermore, a linear systolic-array system with content addressable memory (CAM) is designed which can use the advantage of matrix sparseness to reduce the overall computation time. A partition scheme for the linear systolic-array system is also proposed to match the limitation of the pin number and the chip area. Finally, the cost and performance of all the class of systolic-array systems for solving linear state equations are illustrated.

Design of a systolic array system for linear state equations

A systolic array system for linear state equations is presented. The Gauss-Jordan algorithm and the matrix-vector multiplicationaccumulation are chosen to solve this problem. For systematically designing the systolic arrays system, the dependence graph (DG) approach has to be extended. The two dependence graphs which represent two different but data-dependent process algorithms are first linked together. Tag bits are added to index nodes in this linked DG which will use to indicate the different functions to be executed in a single processor element (PE). By applying the conventional time-scheduling and node-assignment procedures on this DG with a tag, the interfacing communication problem of a systolic arrays system will be well solved and the control of the diferent functions of the PE can be distributed throughout the array. Based on this method, an optimal linear state solver has been designed successfully.

Bit-level systolic array implementation of the winograd fourier transform algorithm

A bit level systolic array system is proposed for the Winograd Fourier transform algorithm. The design uses bit-serial arithmetic and, in common with other systolic arrays, features nearest-neighbour interconnections, regularity and high throughput. The short interconnections in this method contrast favourably with the long interconnections between butterflies required in the FFT. The structure is well suited to VLSI implementations. It is demonstrated how long transforms can be implemented with components designed to perform a short length transform. These components build into longer transforms preserving the regularity and structure of the short length transform design.