Systolic Arrays For Matrix Multiplication Research Articles

Latency Analysis in the 2-Dimensional Systolic Arrays for Matrix Multiplication

This paper deals with the latency analysis in a twodimensional systolic array for matrix multiplication. The latency for all possible connection schemes is discussed. In this way there is obtained the lower bound of the latency that can be achieved using such arrays.

Design of Linear Systolic Arrays for Matrix Multiplication

This paper presents architecture for matrix multiplication optimized to be integrated as an accelerator unit to a host computer. Two linear systolic arrays with unidirectional data flo ...

A class of fault-tolerant systolic arrays for matrix multiplication

This paper presents a proposal for a systematic approach for designing one class of fault-tolerant systolic arrays with orthogonal interconnects and unidirectional data flow (OUSA) for multiplication of rectangular matrices. The method employs space-time redundancy to achieve fault-tolerance. It consists of four steps. In the first step the inner computation space of the basic systolic algorithm for matrix multiplication is expanded. In the second step we derive a matrix multiplication algorithm which enables us to obtain OUSAs with data pipeline period λ = 3 . During the third step redundancy is introduced by deriving three equivalent algorithms with disjoint index spaces. In the last step the obtained algorithm is mapped into a processor-time domain. In this way we have obtained four different OUSAs. For the given matrix dimensions, two out of four arrays have an optimal number of processing elements (PEs) and minimal execution time. For the square case, all arrays have an optimal number of PEs, Ω = n ( n + 2 ) , and total execution time of T t o t = 6 n . All of them can tolerate single transient errors and the majority of multiple error patterns with high probability. In addition, two arrays can tolerate permanent faults as well. The obtained arrays are suitable for implementation in VLSI technology. Compared to a hexagonal array of the same dimensions, the number of I/O pins is reduced by approximately 30%.

Block matrix multiplication and lu factorisation systolic arrays

The Kung Leiserson [1] systolic array for matrix multiplication and LU factorisation is re-examined and the principle of explicit block matrix computation is extended to higher block matrix multiplication and LU factorisation schemes and multi-layer systolic arrays.

Nineteen ways of systolic matrix multiplication

In this paper, we have designed nineteen systolic arrays for matrix multiplication under the frame work of the systolic synthesis method using regular iterative algorithm (RIA) representation. Then we define different systolic array performance measures in order to evaluate the systolic designs. The performance of the designed systolic arrays is analysed in details and this allows the comparison among the different systolic designs.

The design of optimal planar systolic arrays for matrix multiplication

The objective of this paper is to provide a systematic methodology for the design of space-time optimal pure planar systolic arrays for matrix multiplication. The procedure is based on data dependence approach. By the described procedure, we obtain ten different systolic arrays denoted as S 1 to S 10 classified into three classes according to interconnection patterns between the processing elements. Common properties of all systolic array designs are: each systolic array consists of n 2 processing elements, near-neighbour communications, and active execution time of 3 n − 2 time units. Compared to designs found in the literature, our procedure always leads to systolic arrays with optimal number of processing elements. The improvement in space domain is not achieved at the cost of execution time or PEs complexity. We present mathematically rigorous procedure which gives the exact ordering of input matrix elements at the beginning of the computation. Examples illustrating the methodology are shown.

On synthesizing optimal family of linear systolic arrays for matrix multiplication

The authors describe a family of linear systolic arrays for matrix multiplication exhibiting a tradeoff between local storage and the number of processing elements (PEs). The design consists of processors hooked into a linear array with each processor having storage s, 1<or=s<or=n, for n*n matrix multiplication, where the number of processors equals n times the least integer >or=n/s. The input matrices are fed as two speed data streams using fast and slow channels to satisfy the dependencies in the usual matrix multiplication algorithm. While a family of linear arrays have been synthesized for this problem, this technique leads to simpler designs with fewer number of processors and improved delay from input to output. All these designs use the optimal number of processors for local storage in the range 1<or=s<or=n. The data flow is unidirectional, which makes the designs implementable on fault wafer scale integration models.<<ETX>>

An even faster systolic array for matrix multiplication

We propose a two-layered mesh array for matrix multiplication which is faster than all previously published arrays in the literature. We map Winograd's algorithm onto a systolic array composed of 0.5 n 2 multiply-and-add cells which can compute the product of two n × n matrices within 1.5 n time-steps.

On a case of symbiosis between systolic arrays

The paper studies the problem of efficiently computing the product of three n × n matrices using O( n 2) elementary processors in O( n) time. The problem is relevant in image processing. After a critical analysis of extensions on well-known systolic arrays for matrix multiplication to solve the proposed problem, a systolic system is disclosed, which achieves the optimal VLSI-complexity AT 2 = O( n 4).