System-on-chip Benchmark Research Articles

Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm

System-on-Chip (SoC) is a structure in which semiconductor components are integrated into a single die. As a result, testing time should be reduced to achieve a low cost for each chip. Effective test scheduling can reduce the SoC testing time, which is more challenging due to its complexity. In this paper, the modified BAT algorithm-based test scheduling is proposed. Testing is carried out on the SoC ITC’02 benchmark circuits. The Modified Bat method is a recently heuristic algorithm that performs global optimization by imitating bat echolocation. Compared to other state-of-the-art algorithms, the Modified BAT Optimization method reduces testing time on SoCs. This paper improves the algorithm’s exploration process by adjusting the equation for bat loudness (A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> ) and pulse emission rate (r). The modified BAT algorithm converges to the optimal solution faster. It has been used in 14 international standard test functions. The test results indicate that the modified BAT algorithm has a fast convergence speed, which minimizes the testing time compared to other evolutionary algorithms on the ITC’02 SoC benchmark circuits.

Wrapper scan chain design algorithm for testing of embedded cores based on chaotic dragonfly algorithm

As embedded pre-designed and pre-validated cores in system-on-chip (SoC) designs have increased usage, the wrapper scan chain design (WSCD) for the embedded cores is one of the fundamental ways to reduce the SoC test time. In this paper, a chaotic dragonfly algorithm (CDA) for WSCD is proposed to minimize the test time of embedded cores by balancing the packaged scan chains (WSCs).Since the WSCD problem is non-continuous, we improve the dragonfly algorithm (DA) with integer coding to make it suitable for the WSCD problem. In order to improve population diversity and prevent falling into local optimum state, we introduce chaotic strategy into DA. Furthermore, a repaired operator that considers the specific knowledge is added to the DA. Since the CDA is a swarm intelligence method, it is expected to effectively solve the NP-hard problem. The experimental results on ITC’02 SoC benchmark show that the proposed algorithm can improve the balanced results and shorten the test time compared with the existing algorithms.

TSV Optimized Test Wrapper Design for Fine Grain Partitioned 3D System on Chip

The 3D System-on-chip (SoC) technology supports the vertical interconnectivity required for the purpose of functional, supply and test access purposes through the use of Through Silicon Vias (TSVs). Little number of available TSVs for test purpose necessitates the optimization of test infrastructure. This paper proposes an algorithm to design the test wrapper for the 3D cores such that the number of the TSVs used per TAM chain are minimized. Test time optimization is done by balancing the lengths of the individual Wrapper chain inside the core. The proposed heuristic firstly distributes the different core elements on the given TAM chains and then uses a diagraph for their insertion ordering to get minimum possible TSV utilization. Simulation results are presented for the different cores of the ITC’02 SoC benchmark circuits. Results show that TSVs can be reduced to 20-30 percent with around 60-70 percent reduction in CPU time utilization for heavy SoCs in comparison to the other proposed techniques.

Test scheduling of System-on-Chip using Dragonfly and Ant Lion optimization algorithms

Test scheduling of System-on-Chip (SoC) is a major problem solved by various optimization techniques to minimize the cost and testing time. In this paper, we propose the application of Dragonfly and Ant Lion Optimization algorithms to minimize the test cost and test time of SoC. The swarm behavior of dragonfly and hunting behavior of Ant Lion optimization methods are used to optimize the scheduling time in the benchmark circuits. The proposed algorithms are tested on p22810 and d695 ITC’02 SoC benchmark circuits. The results of the proposed algorithms are compared with other algorithms like Ant Colony Optimization, Modified Ant Colony Optimization, Artificial Bee Colony, Modified Artificial Bee Colony, Firefly, Modified Firefly, and BAT algorithms to highlight the benefits of test time minimization. It is observed that the test time obtained for Dragonfly and Ant Lion optimization algorithms is 0.013188 Sec for D695, 0.013515 Sec for P22810, and 0.013432 Sec for D695, 0.013711 Sec for P22810 respectively with TAM Width of 64, which is less as compared to the other well-known optimization algorithms.

Test scheduling for system on chip using modified firefly and modified ABC algorithms

The system-on-chip (SoC) is an integration of millions of electronic components, there is always a chance for faults to occur due to manufacturing defects. In order to solve this problem, it is essential to test the manufactured chips. The time spent on testing increases the testing cost which reflects on the cost of the chip. While testing the SoC, core accessibility and testing time are the main issues to be considered. In order to reduce the testing time, test scheduling has to be performed in an effective manner. In this article ACO, Modified ACO, ABC, Modified ABC, Firefly and Modified Firefly test scheduling algorithms were tested on two SoC benchmark circuits. Experimental results show that the Modified ABC algorithm performs better than the other algorithms used in test scheduling. When compared with ACO, Modified ACO, ABC, Firefly and Modified Firefly algorithms, the Modified ABC algorithm’s testing time has been reduced by 82%, 69%, 25%, 43% and 48% for d695 SoC and 80%, 73%, 20%, 41% and 47% for p22810 SoC benchmark circuits respectively.

Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling

With shrinking device sizes, System-on-Chip (SoC) cores are growing in number and complexity. This has led to high volumes of test data and long test times. Therefore, reducing test cost by minimizing the overall test time is one of the main goals of SoC testing. To efficiently manage test resources and power dissipation, tests for the SoC cores are arranged into test schedules. Traditional SoC test methods assume a constant test frequency and supply voltage (VDD) for the entire test schedule. However, test power and test time can be regulated by varying VDD and test clock frequency to optimize SoC test schedules for a given power budget. The research presented in this paper focuses on power-aware optimization of SoC test schedules to minimize test time by scaling the supply voltage and test clock rate. This scaling can be on a per session basis (in case of session-based test schedules) or dynamically (in case of sessionless test schedules). Exact and heuristic algorithms for solving the optimization problem are discussed. These algorithms are implemented and applied to several SoC benchmarks. Results show a significant reduction in SoC test time over the conventional test schedules where VDD and clock are fixed at given nominal values.

A Novel Massively Parallel Testing Method Using Multi-Root for High Reliability

Wafer testing (wafer sort) is used in the semiconductor industry to reduce test costs. High parallelism is important to reduce test application time. However, increasing parallelism is becoming more difficult because the elements that drive test costs are increases in the pin count of the system on chip (SOC), and required automated test equipment (ATE) channels. While the need for parallelism has been growing, a reliability problem in which fault distribution causes good devices under test (DUT) to be improperly tested is becoming a concern. To achieve high parallelism and reliability, we propose a novel, massively parallel testing method using multi-root. In addition, we develop a test setup for setting the root-DUT location and the path of all DUTs. Using the proposed wafer testing method, test data can be transferred between the ATE and dies using multi-roots. The experimental results using ITC 02 SOC benchmarks show that the proposed method can reduce test costs up to 90%, and achieve nearly 94.84% test reliability without affecting yield.

Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm

The current semiconductor technology allows integration of all components onto a single chip called system-on-chip (SoC), which scales down the size of product and improves the performance. When a system becomes more complicated, testing process, such as test scheduling, becomes more challenging. Recently, peak power has also been considered as constraints in the test scheduling problem. Besides these constraints, some add-on techniques including pre-emption and non-consecutive test bus assignment have been introduced. The main contribution of each technique is the reduction of idling time in the test scheduling and thus reducing the total test time. This paper proposes a power-aware test scheduling called enhanced rectangle packing (ERP). In this technique, we formulate the test scheduling problem as the rectangle packing with horizontally and vertically split-able items (rectangles) which are smaller to fill up more compactly the test scheduling floor plan. Experimental results conducted on ITC’02 SoC benchmark circuits revealed positive improvement of the power-aware ERP algorithm in reducing total SoC test time.

Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips

Network-on-Chips (NoCs) have been proposed as a solution for addressing the global communication challenges in System-on-Chip (SoC) architectures that are implemented in nanoscale technologies. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, power- efficient NoC topology that satisfies the application characteristics is required. In this work, we present a design methodology that automates the synthesis of such application-specific NoC topologies. We present a method which integrates partitioning into floorplanning phase to explore optimal clustering of cores during floorplanning with minimized link and switch power consumption. Based on the size of applications, we also present an Integer Linear Programming and a heuristic method to place switches and network interfaces on the floorplan. Then, a power and timing aware path allocation algorithm is carried out to determine the connectivity across different switches. We perform experiments on several SoC benchmarks and present a comparison with the latest work. For small applications, the NoC topologies synthesized by our method show large improvements in power consumption (27.54%), hop-count (4%) and running time (66%) on average. And for large applications, the synthesized topologies result in large power (31.77%), hop-count (29%) and running time (94.18%) on average.

Test Scheduling Method Based on Cellular Genetic Algorithm for System on Chip

The main aspects for the test of system on chip (SoC) are designing testability architectures and solving the test scheduling. The test time of SoC can be reduced by using good test scheduling schemes. A test scheduling method based on cellular genetic algorithm is presented in this paper. In the method, the individuals are used to represent the feasible solutions of the test scheduling problem, the individuals are distributed over a grid or connected graph, the genetic operations such as selection and mutation are applied locally in some neighborhood of each individual. The test scheduling schemes are obtained by carrying out the evolutionary operations for the populations. A lot of experiments are performed for the SoC benchmark circuits, the experimental results show that the better test scheduling schemes can be obtained by the method in this paper.

Indirect Test Architecture for SoC Testing

A generic model for test architectures in the core-based system-on-chip (SoC) designs consists of source/sink, wrapper, and test access mechanism (TAM). Current test architectures for digital cores assume a direct connection between the core and the tester. In these architectures, the tester establishes a physical link between itself and the core, such that it can directly control the core's design-for-testability (DFT), such as the scan chains or primary inputs. This direct connection undermines the modularity in the generic test architecture by tightly coupling its elements. In this paper, we propose a network-oriented indirect and modular architecture (NIMA) for postfabrication test in an SoC design methodology. In NIMA, test stimuli and expected results for digital cores are first compiled into new formats and subsequently encapsulated into packets. These packets are augmented with control and address bits such that they can autonomously be transmitted to their destination through a switching fabric. Owing to the indirect nature of the connection, embedded autonomous blocks at each core are used to apply the test to the core and compare the test results with expected values. This indirect access to the core decouples test data processing at the core from its communication providing the basis for flexible and modular test design and programming. Moreover, NIMA facilitates remote-access of single or multiple testers to an SoC, and enables the sending of test data to an SoC in-field in order to test the chip in its target system. Finally, NIMA serves in contributing toward the development of new test architectures that benefit from network-centric SoCs. We present a first implementation of NIMA when applied to a number of SoC benchmarks.