Synthesis Of Symmetric Functions Research Articles

Use of Symmetric Functions Designed by QCA Gates for Next Generation IC

Different logic gates like MV, NOT, AOI, NNI etc under QCA nanotechnology are introduced. NNI gate is highly effective regarding space and speed consideration. Any Boolean functions, confined in thirteen number standard Boolean functions, are synthesized by MV and NNI gates or simply NNI gates alone, eliminating inverter (NOT) gate. A new method for realizing symmetric functions in binary reversible logic is introduced. My procedure synthesizes for a more efficient realization both the unate and non unate symmetric functions with little garbage. The method is used in a classical logic. I use only 2-inputs and 2-outputs AND- NAND and OR-NOR cells designed on QCA technology. It admits a recursive construction. Ultimately I achieve a general equation for the minimum number of gates required to an arbitrary number of input variables, causing synthesis of symmetric function. These symmetric functions consist of different Boolean functions with adder circuits functions, subsequently all other combinational circuits like subtractor, multiplier, divisor, multiplexer, encoder, comparator etc can be designed by the adder circuit only which ensures next generation IC design. It provides a significant reduction in hardware cost and switching delay compared to other existing techniques.

Digital Combinational Circuits Design with the Help of Symmetric Functions Considering Heat Dissipation by Each QCA Gate

Different logic gates like MV, NOT, AOI, NNI etc under QCA nanotechnology are introduced. NNI gate is highly effective regarding space and speed consideration. In earlier work, realizing symmetric functions in binary reversible logic is studied. In that, 2-inputs and 2-outputs AND-NAND and OR-NOR cells are designed. Ultimately a general equation for the minimum number of gates required to an arbitrary number of input variables causing synthesis of symmetric function is achieved. In current work, I compare the heat dissipation due to the garbage outputs for designing different combinational digital circuits with the help of symmetric functions realized circuits. It provides a significant reduction in hardware cost and switching delay with respect to the other existing techniques.

Testable Design of Digital Summation Threshold Logic Array for Synthesis of Symmetric Functions

A new cellular array is introduced for synthesizing totally symmetric Boolean functions. The cellular structure uses only 3-input, 3-output AND–ORcells, and is fully path-delay fault testable. It is an improved version of the classical digital summation threshold logic array used earlier in logic design [1]. It admits a universal test set of length 2n that detects all single stuck-at faults, wheren is the number of input variables. The proposed design is useful in view of the fact that two-level realizations of most of the symmetric functions are known to be path-delay untestable. Experiments on several circuits demonstrate that the structure offers less area and fewer number of paths compared to earlier delay testable proposals.

Synthesis of Symmetric Switching Functions Using Threshold Logic Elements

The problem of minimal multilevel synthesis of symmetric switching functions with threshold logic elements is studied. A weight matrix representation of a threshold logic network is given. A number of theorems are presented which give necessary and sufficient conditions for minimal synthesis of symmetric functions with a maximum of eight positive transitions. In each case the minimal network is specified. An example has been worked out.