Synthesis Of Sequential Circuits Research Articles

Sequential Circuits Synthesis for Rapid Single Flux Quantum Logic Based on Finite State Machine Decomposition

Rapid Single Flux Quantum (RSFQ) logic is a promising technology to supersede Complementary metal-oxidesemiconductor (CMOS) logic in some specialized areas due to providing ultra-fast and energy-efficient circuits. To realize a large-scale integration design, electronic design automation (EDA) tools specialized for RSFQ logic are required due to the divergences in logic type, timing constraints, and circuit structure compared with CMOS logic. Logic synthesis is crucial in converting behavioral circuit description into a circuit netlist, typically combining combinational and sequential circuit synthesis. For the RSFQ logic, the sequential circuit synthesis is challenging, especially for non-linear sequential blocks with feedback loops. Thus, this paper presents a sequential circuit synthesis algorithm based on finite state machine (FSM) decomposition, which ensures design functionality, lowers costs, and improves the RSFQ circuit performance. Additionally, we present the synthesis processes of the feedback logic and the 2-bit counter to demonstrate how the proposed algorithm operates, and ISCAS89 benchmark circuits reveal our method’s ability to synthesize large-scale sequential circuits.

Efficient designs of reversible sequential circuits

Recently, the synthesis of reversible sequential circuits has attracted researchers’ attention for implementing low-power logic designs. So far, the direct and replacement techniques have been used in the reversible sequential circuits design. The replacement technique leads to high quantum cost. There is the principle to look for efficient reversible circuits composed of Clifford + T gates by optimizing quantum cost, the number of T gates, and particularly the T-depth of the circuit, which depends on the type and layout of the reversible gates used in the function. This paper has proposed an optimized version of direct feedback technique without any flip-flops and is performed on several samples of reversible circuits design, such as counters and shift registers. It has been shown that by partial changes in the direct technique, quantum cost and other cost metrics have been improved. It has also displayed some efficient designs of the reversible parallel-to-serial converter with parity capability and low-cost design of the control unit for a reversible self-controlled serial adder system. The analysis and comparison depict that all new proposed designs have optimized the existing works in terms of performance variables, including quantum cost, number of T gates, and T-depth of the circuit.

A Probabilistic Tabu Search State Assignment Algorithm for Area and Power Optimization of Sequential Circuits

State assignment is the most critical step in the synthesis and optimization of sequential circuits as it significantly impacts sequential circuits area and power. Due to the high complexity of the state assignment problem and the ineffectiveness of existing deterministic algorithms in generating good solutions, evolutionary algorithms can be employed to obtain more effective state assignment solutions. In this paper, we propose a probabilistic tabu search (PTS) state assignment algorithm that is employed for the optimization of area and power of sequential circuits. The proposed algorithm is based on tabu search with the addition of exploiting code swap probabilities to prune the search space more effectively. Code swap probabilities are updated dynamically during the execution of the algorithm in such a way that code swaps that result in relatively inferior solutions will be assigned lower probabilities while those that result in good solutions will be assigned higher probabilities. In addition, tabu list size is changed dynamically during execution to help the algorithm get out of local minima. Based on experimental results, we show that the proposed PTS state assignment algorithm is more effective than all existing state assignment algorithms as it generates state assignment solutions with significantly lower area and power.

Novel Characterizations of the JK Bistables (Flip Flops)

The JK flip flop is a flexible type of bistable elements that has extensive uses in digital electronics and control circuits. It is usually described by its characteristic equation or next-state table (used for analysis purposes) and its excitation table (used for synthesis purposes). This paper explores a variety of novel characterizations of JK flip flops. First, equational and implicational descriptions are presented, and methods of logic deduction are utilized to produce complete statements of all propositions that are true for a general JK flip flop. Next, methods of Boolean-equation solving are employed to find all possible ways to express the excitations in terms of the present state and next state. The concept of Boolean quotient is used to impose certain requirements so as to find particularly useful expressions of the excitations. Relations of JK flip flops to other types of flip flops are also explored. This paper is expected to provide an immediate pedagogical benefit, and to help facilitate the analysis and synthesis of sequential digital circuits.

Linear Logic Synthesis of Multi-Valued Sequential Circuits

Linear Logic Synthesis of Multi-Valued Sequential Circuits

Two Novel Characterizations of the DE Flip Flop

Modern digital circuits, especially those based on large-scale integration devices employ DE flip flops, which are an extension of the D type with the capacity to store an input value only upon request or enabling. The DE flip flop could possibly be described algebraically by its characteristic equation or tabularly by its next-state table (used for analysis purposes) and its excitation table (used for synthesis purposes). This paper explores two novel characterizations of DE flip flops. First, equational and implicational descriptions are presented, and the Modern Syllogistic Method is utilized to produce complete statements of all propositions that are true for a general DE flip flop. Next, methods of Boolean-equation solving are employed to find all possible ways to express the excitations in terms of the present state and next state. The concept of Boolean quotient plays a crucial role in exposing the pertinent concepts and implementing the various desired derivations. This paper is expected to be of an immediate pedagogical benefit, and to facilitate the analysis and synthesis of contemporary sequential digital circuits.

First Steps in Creating Online Testable Reversible Sequential Circuits

Synthesis of reversible sequential circuits is a very new research area. It has been shown that such circuits can be implemented using quantum dot cellular automata. Other work has used traditional designs for sequential circuits and replaced the flip-flops and the gates with their reversible counterparts. Our earlier work uses a direct feedback method without any flip-flops, improving upon the replacement technique in both quantum cost and ancilla inputs. We present here a further improved version of the direct feedback method. Design examples show that the proposed method produces better results than our earlier method in terms of both quantum cost and ancilla inputs. We also propose the first technique for online testing of single line faults in sequential reversible circuits.

From high-level modeling toward efficient and trustworthy circuits

Behavior–interaction–priority (BIP) is a layered embedded system design and verification framework that provides separation of functionality, synchronization, and priority concerns to simplify system design and to establish correctness by construction. BIP framework comes with a runtime engine and a suite of verification tools that use D-Finder and NuSMV as model-checkers. In this paper, we provide a method and a supporting tool that take a BIP system and a set of invariants and compute a reduced sequential circuit with a system-specific scheduler and a designated output that is \(\mathtt {true}\) when the invariants hold. Our method uses ABC, a sequential circuit synthesis and verification framework, to (1) generate an efficient circuit implementation of the system that can be readily translated into FPGA or ASIC implementations and to (2) verify the system and debug it in case a counterexample is found. Moreover, we generate a concurrent C implementation of the circuit that can be directly used for runtime verification. We evaluated our method with two benchmark systems, and our results show that, compared to existing techniques, our method is faster and scales to larger sizes.

State assignment for area minimization of sequential circuits based on cuckoo search optimization

A major optimization problem in the synthesis of sequential circuits is State Assignment or State Encoding in Finite State Machines (FSMs). The state assignment of an FSM determines the complexity of its combinational circuit and thus area, delay, testability and power dissipation. Since optimal state assignment is an NP-hard problem and existing deterministic algorithms produce solutions far from best known solutions, we resort to the use of non-deterministic iterative optimization heuristics. This paper proposes the use of cuckoo search optimization (CSO) algorithm for solving the state assignment problem (SAP) of FSMs with the aim of minimizing area of the resulting sequential circuit. Results obtained from the CSO algorithm are compared with those obtained from binary particle swarm optimization (BPSO) algorithm, genetic algorithm (GA), and the well-known deterministic methods of NOVA and JEDI. The results indicate that CSO outperforms deterministic methods as well as other non-deterministic heuristic optimization methods.

Design of Reversible Counter

This article presents a research work on the design and synthesis of sequential circuits and flip-flops that are available in digital arena; and describes a new synthesis design of reversible counter that is optimized in terms of quantum cost, delay and garbage outputs compared to the existing designs. We proposed a new model of reversible T flip-flop in designing reversible counter

Binary particle swarm optimization (BPSO) based state assignment for area minimization of sequential circuits

State assignment (SA) for finite state machines (FSMs) is one of the main optimization problems in the synthesis of sequential circuits. It determines the complexity of its combinational circuit and thus area, delay, testability and power dissipation of its implementation. Particle swarm optimization (PSO) is a non-deterministic heuristic that optimizes a problem by iteratively trying to improve a candidate solution with regard to a given measure of quality. PSO optimizes a problem by having a population of candidate solutions called particles, and moving them around in the search-space according to a simple mathematical formulae. In this paper, we propose an improved binary particle swarm optimization (BPSO) algorithm and demonstrate its effectiveness in solving the state assignment problem in sequential circuit synthesis targeting area optimization. It will be an evident that the proposed BPSO algorithm overcomes the drawbacks of the original BPSO algorithm. Experimental results demonstrate the effectiveness of the proposed BPSO algorithm in comparison to other BPSO variants reported in the literature and in comparison to Genetic Algorithm (GA), Simulated Evolution (SimE) and deterministic algorithms like Jedi and Nova.

Synthesis and optimization of multiple-valued combinational and sequential reversible circuits with don't cares

In this paper, a synthesis method for combinational multiple-valued reversible logic (MVRL) circuits is proposed. This algorithm can use the don't care values in the synthesis process to obtain the optimal circuit with respect to quantum cost. The binary Fredkin gate is extended to the MVRL Fredkin gate, and its synthesis using 2×2 gates is proposed. Additionally, we have used the algorithm to design sequential MVRL circuits based on the state transition table. We propose three generalized designs for T, D, and JK flip flops (FF). The generalized r-valued T-FF is designed using 2r−3 controlled Cycle gates (r stands for radix). The r-valued D-FF is designed using the new version of the MVRL Fredkin gate. The ternary JK-FF, which performs nine distinct functions, is designed using only seven controlled Cycle gates. These FFs are the essential circuits to design MVRL state machines, and we synthesize the circuits with the minimal number of constant inputs and garbage outputs.

An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting

This paper presents a finite-state machine (FSM) reengineering method that enhances the FSM synthesis by reconstructing a functionally equivalent but topologically different FSM based on the optimization objective. This method enables the FSM synthesis algorithms to explore a set of functionally equivalent FSMs and obtain better solutions than those in the original FSM. To demonstrate the effectiveness of the proposed method, we apply it to popular power- and area-driven FSM synthesis algorithms, respectively. Our method achieves an average of 5.5% power reduction and 2.7% area reduction, respectively, on 25 Microelectronics Center of North Carolina (MCNC) FSM benchmarks, where the proposed method is applicable. This is a significant performance improvement for the power- and area-driven FSM synthesis algorithms being used. Our method has a negligible run-time overhead, and it maintains the quality of the synthesis solutions.

A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits

A method of sequential circuit synthesis is proposed for Single-Flux-Quantum (SFQ) digital circuits. Since all logic gates of SFQ digital circuits are driven by a clock signal, methods of sequential circuit synthesis for semiconductor digital circuits cannot derive the full power of high-throughput computation of SFQ circuit technology. In the method, a 'state module' consisting of a DFF and several AND gates is used. First, states of a sequential machine are encoded by one-hot encoding and state modules are assigned to the states one-by-one, and then, the modules are connected with each other according to the state transition. For the connection, Confluence Buffers (CBs), i.e., merger gates without clock signals are used. Consequently, gates driven by a clock signal are removed from its feedback loops, and therefore, a high-throughput SFQ sequential circuit is achieved. The experimental results on benchmark circuits show that compared with a conventional method for semiconductor digital circuits, the proposed method synthesizes circuits that work with 4.9 times higher clock frequency and have 17.3% more gates on average.

Synthesis of sequential circuits by using linearization

The paper deals with synthesis of sequential circuits defined by their algorithmic state machine notation. Such circuits have a number of specific properties which enable efficient design of the circuits by utilizing so-called linearization techniques. A typical linearization technique includes calculation of autocorrelation values for a system of logic functions corresponding to the circuit. For the mentioned sequential circuits, the calculations which usually require massive computational recourses may be significantly reduced and thus low-overhead implementations of the circuits can be obtained relatively easy. The paper introduces a novel architecture of so-called linearized sequential circuits, and a piece-wise linearization approach for synthesis of sequential circuits. Results are evaluated both analytically and by using a number of standard benchmarks.

Testable synthesis of synchronous sequential circuits considering strong-connectivity using undefined states

In this paper, usage of undefined states on a state transition graph (STG) is addressed to obtain high fault coverage, in the area of synthesis for testability (SFT) of synchronous sequential circuits. Basically, a given STG could be modified by adding undefined states and distinguishable transitions so that each state might be included in one strongly-connected component as much as possible. Such modification has an effect on decreasing the number of redundant faults because redundant faults caused by the existence of unreachable states on an STG may be eliminated. For the modification, we propose two algorithms for both incompletely specified STGs and completely specified STGs, respectively. In the case of incompletely specified STGs, undefined states are added using unspecified transitions of defined states. In the case of completely specified STGs, undefined states are added by changing transitions specified on an STG while preserving state equivalence. Experimental results with MCNC benchmarks show that the number of redundant faults of gate-level circuits synthesized by our modified STGs are reduced, resulting in high fault coverage as well as short test generation time.

General decomposition of incompletely specified sequential machines with multi-state behavior realization

This paper is devoted to decomposition of sequential machines, discrete functions and relations. Sequential machine decomposition consists in representation of a given machine as a network of collaborating partial machines that together realize behavior of the given machine. A good understanding of possible decomposition structures and of conditions under which the corresponding structures exist is a prerequisite for any adequate circuit or system synthesis. The paper discusses the theory of general decomposition of incompletely specified sequential machines with multistate behavior realization. The central point of this theory is a constructive theorem on the existence of the general decomposition structures and conditions under which the corresponding structures exist. The theory of general decomposition presented in this paper is the most general known theory of the binary, multi-valued and symbolic sequential and combinational discrete network structures. The correct circuit generator defined by the general decomposition theorem covers all other known structural models of sequential and combinational circuits as its special cases. Using this theory, in recent years we developed a number of effective and efficient methods and EDA tools for sequential and combinational circuit synthesis that consistently construct much better circuits than other academic and commercial state-of-the-art synthesis tools. This demonstrates the practical soundness of our theory. This theory can be applied to any sort of binary, multi-valued and symbolic systems expressed as networks of relations, functions or sequential machines, and can be very useful in such fields as circuit and architecture synthesis of VLSI systems, knowledge engineering, machine learning, neural network training, pattern analysis, etc.

Fast and compact sequential circuits for the FPGA-based reconfigurable systems

Reconfigurable systems fill the flexibility, performance, power dissipation, and development and fabrication cost gap between the application specific systems implemented with hard-wired application specific integrated circuits and systems based on the standard (general purpose) programmable microprocessors. During the last decade they became the mainstream implementation technology for custom computation and embedded system products in such fields as telecommunication, image processing, video processing, multimedia, DSP, cryptography, embedded control, etc. To efficiently develop, implement and use the reconfigurable systems, adequate computer-aided support tools are necessary. Since most reconfigurable systems are implemented using the look-up table (LUT) field programmable gate arrays (FPGA) technology, the circuit synthesis tools targeting this technology are of primary importance for their effective and efficient implementation. In this paper, a new sequential circuit synthesis methodology is discussed that targets LUT FPGAs and FPGA-based reconfigurable system-on-a-chip platforms. The methodology is based on the information-driven approach to circuit synthesis, general decomposition and theory of information relationship measures that we previously developed. Our synthesis methods considerably differ from all other known methods. The experimental results from the automatic circuit synthesis tools that implement our methods demonstrate that the information-driven approach consistently applied in the whole sequential circuit synthesis chain efficiently produces very fast and compact sequential circuits.

Using binary decision diagrams for representation and analysis of communication protocols

A symbolic representation of a state/transition system based on binary decision diagrams (BDDs) is generally more compact than an explicit representation like a state/transition table. This is due to regular and repetitive patterns occurring in state/transition systems. By exploiting this property, huge state spaces can be represented, and the resulting BDDs can be profitably used for activities such as symbolic model checking and sequential circuit synthesis. This paper shows how such techniques can be applied to communication protocols by presenting a systematic method to build BDD representations from protocol specifications expressed in the ISO standard protocol specification language LOTOS. The method exploits the compositionality of the process algebra of LOTOS to avoid the enumeration of all the states and transitions, takes also data into account, enables building the BDDs in the more convenient disjunctive partitioned form, and can handle any LOTOS specification characterized by a finite LTS. The method consists in partitioning the set of process definitions according to their mutual recursion relationships, building an LTS for each set of mutually recursive process definitions, encoding these LTSs as BDDs which in turn are combined together, according to the process algebraic operators, to obtain the overall BDD representation. An example is used throughout the paper to illustrate the method.

State assignment of finite-state machines

The state-assignment problem of finite-state machines (FSMs) is addressed. State assignment is a mapping from the set of states (symbolic names) of an FSM to the set of binary codes with the objective of minimising the area of the combinational circuit required to realise the FSM. It is one of the most important optimisation problems in the automatic synthesis of sequential circuits since it has a major impact on the area, speed, power and testability of the circuits. The problem of finding an optimal state assignment is NP-hard. A new scheme is presented based on mean-field annealing (MFA) to solve the graph-embedding problem which is the main step in the state-assignment process. The MFA algorithm combines the characteristics of the simulated annealing and the Hopfield neural network. To solve the problem by MFA, the graph-embedding problem is mapped into a neural network and an energy function is formulated. Experiments over the MCNC FSM benchmarks demonstrate that the proposed MFA algorithm can produce superior results compared with the specialised methods such as the MUSTANG, NOVA and genetic algorithm.