Synchronous Sequential Machines Research Articles

Design of Smart Traffic Signal using Verilog

Traffic light control can be designed as synchronous sequential machine with finite number of states. Explicit finite state model is used to design the necessary coding for control system using Verilog HDL. The machine is modeled with only six states necessary delay is provided and for that particular delay the necessary traffic lights are set ON and OFF. For illustration just only two roads Chosen and control algorithm controls the traffic lights of that roads proposes a flexible framework which provides a particular delaying particular using click divider, also discusses the issues of modeling the state machine in a synthes is friendly manner. The proposed system aims to optimize traffic flow and reduce congestion by dynamically adjusting signal timings based on real-time traffic data. The design includes modules for vehicle detection, data processing, and signal control. By utilizing Verilog's capabilities, the system achieves efficient and accurate signal management, enhancing over all traffic management and contributing to safer and more stream lined urban mobility..

Using recurrent neural networks to learn the structure of interconnection networks

A modified Recurrent Neural Network (RNN) is used to learn a Self-Routing Interconnection Network (SRIN) from a set of routing examples. The RNN is modified so that it has several distinct initial states. This is equivalent to a single RNN learning multiple different synchronous sequential machines. We define such a sequential machine structure as augmented and show that a SRIN is essentially an Augmented Synchronous Sequential Machine (ASSM). As an example, we learn a small six-switch SRIN. After training we extract the network's internal representation of the ASSM and corresponding SRIN.

The clause counter map: an event chaining algorithm for online programmable logic

The clause counter map method (CCM) is a software inference engine for programmable logic systems, including logic controllers and knowledge-based information systems. It provides efficient realizations of synchronous sequential machines using two-valued or three-valued logic. CCM permits the use of general purpose processors for large on-line control models. The CCM interpreter is designed to trade space for time. A redundant state is maintained in a compact map form. Logical events percolate through an otherwise static model. This mode of operation distinguishes the class of event chaining algorithms. Prior on-line methods repeatedly reconstruct or test unchanging portions of the model. In large models, CCM can exceed binary decision machines in speed and require less space. Contemporary modeling languages can be translated into CCM models. Thus event chaining implementation is available for control models defined by relay ladder logic, state machines, function charts, and Petri nets. >

Générateur de machines séquentielles autotestables pour circuits intégrés spécifiques

This paper presents an original method using a ROM memory, of systematically synthesizing on-line and offline self-testing synchronous sequential machines (automata, sequencers,), for the design of compiled ASIC’S. Choices about state transition graph coding and circuit architecture are related to simplicity, compactness, operating rate and especially to testability. The on-line and off-line testing is based on an error detecting code of a recurrent type: in addition to useful data, the ROM memory contains redundant information which is distributed between two consecutive states. This method guarantees both present state coherence and past transition conformity. On-line testing is based in this type of coding, called distributed redundancy coding. Its fault coverage is given for different classes of hardware failures. Off-line testing, which is exhaustive, uses the distributed redundancy coding technique and consists in scanning all the possible graph transitions in memory address order.

A State Assignment for p‐Valued Sequential Machines

AbstractFor p‐valued synchronous sequential machines a new method of state assignment is proposed. In this method, a given sequential machine is expressed by a state transition table and then codes with low Hamming weight are assigned to the internal states with high frequency of appearance. This process yields the state transition functions which express transition to the states with low frequency of appearance, thereby attaining the state transition functions with the minimum number of terms in the principal disjunctive canonical form. All the procedures can be expressed in a simple straightforward algorithm and therefore can be processed fast. Experiments on a computer for p = 3 show that the truth‐table densities of the state transition matrices are about 80 to 90 percent compared with those obtained by the triangle method [1, 2] which is one of the existing methods. The results compare favorably with those obtained by other methods even after simplification by the extended Quine‐McCluskey method.

Transition submatrices in regular homing experiments and identification of sequential machines of known class using direct-sum transition matrices

In connection with the measurement and control of synchronous sequential machines, Das et al. recently proposed an approach to the solution of the problems using the transition matrix representation of the machine and its higher-order forms. In the present paper, by extending the transition matrix approach of Das et al., an approach based on transition submatrix is developed to solve the regular homing problem in synchronous sequential machines. In addition, the problem of identifying a machine of a known class is also considered. Since the proposed transition submatrix approach can simplify the matrix computations, and can reduce the amount of storage required by significantly reducing both the dimension and the order of the matrix being used, it not only retains all the advantages of the approach by Das et al., but it lends itself to even easier computer implementations as well.

Further studies on the matrix approach to the measurement and control problems of synchronous sequential machines— Performance evaluation by computer simulation and application of specific heuristics

The sequential machine is a well-established model for discrete information processing devices and systems. Under many circumstances, it is necessary to identify the state of the machine. Usually an appropriate sequence of input symbols is found and fed the machine; then, based on the corresponding output sequence, the state is determined. The major problem lies in finding the input sequence for the experiment. The usual approach to solve this problem is to use the response tree in conjunction with the transition table of the machine under consideration, then determine the growth and truncation of each branch according to a set of rules which necessitates comparison with each existing node. The answer is eventually reached through complying with certain rules. In general, the comparison process is slow and wasteful and there is no way of controlling computing space; also, there is no framework to implement fast solution techniques. In this paper, in order to solve the same problem, the concept of transition table is extended, operations are defined, and, in order to solve the problem quickly, some techniques and heuristics are introduced. This proposed approach can save a lot of computing time and memory space.

A new approach to single-fault-tolerant realization of synchronous sequential machines

This paper develops a new approach to the single-fault-tolerant realization of a given finite-state synchronous sequential machine by computing the correct state of the machine in a non-real-time mode. The computation is performed (by a checking clock pulse of higher frequency than the system clock of the machine) during the time interval between two successive state transitions of the machine. The proposed realization needs much less extra memory elements and associated combinational logic. And only a small portion of the required logic need be fault-tolerant.

On the design of improved failure detection experiments in synchronous sequential machines based on terminal measurements: S. R. Das, Z. Chen, S. M. Wu, S. Y. Lee and A. Bhattacharyya. Computer Elec Engng, 6, 293 (1979)

On the design of improved failure detection experiments in synchronous sequential machines based on terminal measurements: S. R. Das, Z. Chen, S. M. Wu, S. Y. Lee and A. Bhattacharyya. Computer Elec Engng, 6, 293 (1979)

On the design of improved failure detection experiments in synchronous sequential machines based on terminal measurements

On modifying a given sequential machien through augmentation of extra inputs and extra outputs, efficient techniques are developed in the present paper for its fault diagnosis and for the design of checking sequences, taking into consideration the case where faults may cause an increase in the number of states of the machine. Improved bounds on the lengths of checking sequences are also established.

Transition matrices in the measurement and control of synchronous sequential machines

This paper develops a matrix approach to the solution of the measurement and control problems in synchronous sequential machines. The control problem in sequential machines is concerned with finding input sequences that take a given machine from a known initial state to a predesignated terminal state. There may be many different measurement problems of interest in sequential machines. One important measurement problem is the identification of the unknown initial state of the machine, called the initial-state identification problem or diagnosing problem; another important measurement problem is the identification of the terminal state of the machine, known as the terminal-state identification problem or homing problem, of which a special case is the synchronizing problem. These measurement problems may be solved by applying predetermined input sequences to the machine and noting the resulting output sequences. The conventional approach to the solution of these measurement and control problems is to make use of the information contained in the transition table of the machine in conjunction with its response tree, which is basically an exhaustive tree search process. In the present paper, instead of using the transition table and the corresponding response tree, we use only the transition matrix representation of the machine and its higher order forms to solve the aforementioned problems. The suggested approach is very systematic and completely algorithmic, and thus lends itself to easy computer implementation.

Positive Fail-Safe Realization of Synchronous Sequential Machines

The correspondence deals with the fail-safe realization of synchronous sequential machines under the assumption that the next-state functions are in any positive form. This leads to new classes of assignments called positive fail-safe assignment's (PFSA) The feasibility conditions of such assignments are given and systematic procedures are presented for deriving them using k-out-of-n codes.

Transition matrices in multiple preset experiments and initial state identification of synchronous sequential machines

Recently, in connection with the measurement and control of synchronous sequential machines, Das et al. proposed an approach to the solution of the problems using the transition matrix representation of the machine and its higher-order forms. In the proposed approach, however, the authors restricted themselves to only simple and preset experiments. Generally speaking, a simple preset experiment is rather easy to implement, though it suffers from the disadvantage that it tends to be lengthy, and sometimes does not provide the experimenter with the desired information. The letter develops a new approach to the solution of the initial state identification problem or diagnosing problem, which happens to be an important measurement problem in sequential machines through multiple preset experimentation, using the transition-matrix representation of the machine and other related concepts as provided in the paper by Das et al. The present approach, like the one suggested before, is also very systematic and completely algorithmic, and thus lends itself to easy computer implementation.

Programmable Array Realizations of Synchronous Sequential Machines

Cellular-array realizations of switching functions have been studied in order to take advantage of the many design possibilities offered by large-scale integration technology. This paper introduces a class of programmable cellular arrays that can be employed to realize arbitrary synchronous sequential machines. State assignments based upon k-out-of-m codes are employed to give rise to machine excitation and output equations in a consistent functional form suitable for implementation via a cellular structure. The proposed arrays are programmable, which makes possible the capability of re-configuring an array to realize different machines by electronically altering the function implemented by each cell of the array. A synthesis algorithm is presented that will allow the designer to program the array without explicitly deriving excitation and output functions. The synthesis technique is applicable to both Mealy and Moore machines with any number of inputs, outputs, and internal states, and utilizing either delay or trigger flip-flops.

Realization of Fault-Tolerant and Fail-Safe Sequential Machines

Given a synchronous sequential machine M, this correspondence deals with the fault-tolerant realization M of M and also its fail-safe realization M on the assumption that the faults that can occur to the circuitry of M or M are of permanent stuck-at type and the total number of faults can be at most some preset positive integer r. First, the realization of M or M is derived for r = 1 and then the same idea is extended to have the realization for any arbitrary r. It has been shown that the realization of M is such that it is also able to tolerate faults of nonpermanent nature.

Fault diagnosis in sequential circuits

This paper is concerned with the diagnosis of faults in synchronous sequential machines. Faults are defined and classified, the problems of detection and diagnosis are discussed, and a previously presented algorithm for fault detection is outlined. This method obtains testing sequences by forcing the machine into a fault-sensitive situation and examining every possible outcome under any possible fault. The detection algorithm is then modified to diagnose all errors.

Multi-valued circuits in fault detection of binary logic circuits

The paper considers two possibilities of employing multi-valued logic circuits for testing of binary networks. The first augments binary synchronous sequential machines through the addition of permutation inputs with multi-valued outputs. The second embeds binary combinational networks into easily testable ternary ones. Both approaches result in simplified testing procedures.

Design of Reliable Synchronous Sequential Circuits

Fail-safe synchronous sequential machines produce safeside outputs when failures occur within the machine. This correspondence presents a procedure to design such machines using a modification of the on-set equation form originally presented by Tohma et al. [1] and later improved by Diaz et al. [2]. A systematic procedure for state assignment and next-state equation derivation, using partition theory, is presented. From this method an easily calculated upper bound on the number of gates required-to realize a fail-safe circuit is derived.

Unate Cascade Realization of Synchronous Sequential Machines

In this paper the problems associated with the minimal realization of synchronous sequential machines by unate cellular cascades have been studied. Given the sequential machine in the form of a flow table, a systematic procedure is followed to generate all the selectable sets. Compatible sets consisting of these selectable sets are next determined and the different secondary variables are assigned. The nested functional forms of the next-state expressions for these variables are finally established. The proposed method is very systematic and perfectly suited for machine processing.

Spectra of Block Coded Digital Signals

Block codes are multilevel codes of constant length whose codewords are the channel encodings of binary sequences of constant length. The spectral density calculation of pulse trains resulting from the use of these codes is dealt with. Under the assumption that the encoding be represented by a finite-state synchronous sequential machine, by means of homogenous Markov chain theory, the spectral density is evaluated in closed form. Both the continuous and the discrete spectral components are easily obtained as soon as the encoder functions are specified. The result obtained is particularly attractive since the finite-state machine model can be used to represent a broad class of encoding schemes of engineering interest. As an example, the spectral density is calculated in the case of the Franaszek MS-43 code.