Synchronous Network-on-Chip Research Articles

Network on Chip for Consumer Electronics Devices: An Architectural and Performance Exploration of Synchronous and Asynchronous Network-on-Chip-Based Systems

The ever-increasing demand for in-home products, automation, and sharing information over social networks has opened a gateway for consumer electronics (CE) devices. As a result, system on chip (SoC)-based multiprocessor systems are designed to meet the current demand. This article presents the architectural issues of multiprocessor SoCs (MPSoCs) used in CE devices and provides network on chip (NoC)-based multiprocessors as a solution that helps alleviate the performance of CE devices. Asynchronous NoC propounds more throughput and lower latency than synchronous NoC for a specific number of virtual channels (VCs) and cores.

PANE

Communication between different IP cores in MPSoCs and HMPs often results in clock domain crossing. Asynchronous network on chip (NoC) support communication in such heterogeneous set-ups. While there are a large number of tools to model NoCs for synchronous systems, there is very limited tool support to model communication for multi-clock domain NoCs and analyse them. In this article, we propose the P luggable A synchronous NE twork on Chip (PANE) simulator, which allows system-level simulation of asynchronous network on chip (NoC). PANE allows design space exploration of synchronous, asynchronous, and mixed synchronous-asynchronous(heterogeneous) NoC for various system-level NoC parameters such as packet latencies, throughput, network saturation point and power analysis. PANE supports a large range of NoC configurations—routing algorithms, topologies, network sizes, and so on—for both synthetic and real traffic patterns. We demonstrate the application of PANE by using synchronous routers, asynchronous routers, and a mix of asynchronous and synchronous routers. One of the key advantages of PANE is that it allows a seamless transition from synchronous to asynchronous NoC simulators while keeping pace with the developments in synchronous NoC tools as they can be integrated with PANE.

GALS implementation of randomly prioritized buffer-less routing architecture for 3D NoC

Recently, there has been enormous attention given to the network on chip (NoC) because it is scalable compared to the communication bus. Three dimensional (3D) NoC is getting more popular due to the reduction of wire length with that off two dimensional NoC. The router in the NoC is provides communication between the different computational units. In this paper, a two-phase bundled-data handshake latch is used with an asynchronous router. The Mousetrap latch controller forms the basis of this asynchronous router. The major part of the arbiter is to schedule the packet, then deliver to its destination without any loss of the packet. This paper proposes a novel asynchronous 3D lottery routing algorithm which is based on arbitral mechanism. The Lottery routing algorithm distinguishes the different priorities of the input port and makes sure that it responses to the higher priority port. The proposed hardware is implemented using Cadence 180 nm technology. The result shows that the power reduction is about 17% and a slight increase in area and delay of about 2% with respect to synchronous 3D NoC.

A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations

Network-on-Chip (NoC) is a flexible and scalable solution to interconnect multi-cores, with a strong influence on the performance of the whole chip. On-chip network affects also the overall power consumption, thus requiring accurate early-stage estimation and optimization methodologies. In this scenario, the Dynamic Voltage Frequency Scaling (DVFS) technique have been proposed both for CPUs and NoCs. The promise is to be a flexible and scalable way to jointly optimize power-performance, addressing both static and dynamic power sources. Being simulation a de-facto prime solution to explore novel multi-core architectures, a reliable full system analysis requires to integrate in the toolchain accurate timing and power models for the DVFS block and for the resynchronization logic between different Voltage and Frequency Islands (VFIs). In such a way, a more accurate validation of novel optimization methodologies which exploit such actuator is possible, since both architectural and actuator overheads are considered at the same time. This work proposes a complete cycle accurate framework for multi-core design supporting Global Asynchronous Local Synchronous (GALS) NoC design and DVFS actuators for the NoC. Furthermore, static and dynamic frequency assignment is possible with or without the use of the voltage regulator. The proposed framework sits on accurate analytical timing model and SPICE-based power measures, providing accurate estimates of both timing and power overheads of the power control mechanisms.

Design of an Energy-Efficient Asynchronous NoC and Its Optimization Tools for Heterogeneous SoCs

The energy usage of on-chip interconnects is a concern for many system-on-chips targeting portable battery-powered devices. We have designed and evaluated a network-on-chip (NoC) for such an application, including tools to optimize for power and communication latency. Our asynchronous (clockless) network operates with efficient two-phase bundled-data links and four-phase routers. The topology and router floorplan is determined by our tool, ANetGen, which optimizes the network for energy and latency using simulated annealing and force-directed placement methods. We compare our solutions against a traditional synchronous NoC as specified by the COSI-2.0 framework and ORION 2.0 router and wire energy models. Traffic is simulated with SystemC functional models, and messages are generated with a “bursty” self-similar <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</i> -model. Results indicate our asynchronous network was more energy-efficient, lower in area, and provided comparable or superior message latency.

An Asynchronous Power Aware and Adaptive NoC Based Circuit

In complex embedded applications, optimisation and adaptation of both dynamic and leakage power have become an issue at SoC grain. A fully power-aware globally-asynchronous locally-synchronous network-on-chip (NoC) circuit is presented in this paper. Network-on-chip architecture combined with a globally-asynchronous locally-synchronous paradigm is a natural enabler for DVFS mechanisms. The circuit is arranged around an asynchronous network-on-chip providing scalable communication and a 17 Gb/s throughput while automatically reducing its power consumption by activity detection. Both dynamic and static power consumptions are globally reduced using adaptive design techniques applied locally for each synchronous NoC units. No fine control software is required during voltage and frequency scaling. Power control is localized and a minimal latency cost is observed.