Synchronous Design Style Research Articles

Quasi Delay Insensitive Majority Voters for Triple Modular Redundancy Applications

Mission- and safety-critical applications tend to incorporate triple modular redundancy (TMR) in their hardware implementation to reliably withstand the fault or failure of any one of the function modules during normal operation, and the function module may be a circuit or a system. In a TMR implementation, two identical copies of a function module are used in addition to the original function module, and the correct operation of at least two function modules is required. In TMR, the corresponding primary outputs of the three function modules are combined using majority voters, which determine the actual primary outputs based on the Boolean majority. Hence, the majority voter is an important component that is useful for conveying the correct operation of a TMR implementation. In the existing literature, many designs of three-input majority voters for TMR have been discussed. However, most of these correspond to the synchronous design style and just one corresponds to the bundled-data asynchronous design style, which is not delay insensitive and hence non-robust. To our knowledge, a robust delay insensitive design of the three-input majority voter has not been considered. In this context, this article presents the designs of robust quasi delay insensitive (QDI) three-input majority voters based on QDI logic synthesis methods, and analyzes which majority voters are preferable in terms of speed, power, and area. We implement example QDI TMR circuits using a QDI full adder as the function module and QDI majority voters using 32/28 nm complementary metal oxide semiconductor (CMOS) technology. The QDI TMR implementations use the delay insensitive dual rail code for data encoding, and four-phase return-to-zero and four-phase return-to-one handshake protocols for data communication.

Towards Designing Asynchronous Microprocessors: From Specification to Tape-Out

Proceeding miniaturization in the VLSI circuits continues to pose challenges to the conventionally used synchronous design style in microprocessors. These include the distribution of clock in the GHz range, robustness to delay variations, reduction in electromagnetic interference, and energy conservation, to name a few. The asynchronous logic has been known for its ability to address the aforementioned challenges by means of the closed-loop handshake protocols, instead of notorious clock signals. Because of these advantages, there have been numerous attempts on building general and special purpose microprocessors during the last three decades. Still, however, the number of asynchronous processors commercially available is scarce, mainly due to an insufficient electronic design and automation tools support, an ambiguous design flow and testing mechanisms for asynchronous logic and, most importantly, absence of a forum to look for relevant works, explaining the design steps and tools for such microprocessors. This paper is intended to bridge this gap by 1) reviewing the design principles of asynchronous logic, including classification, signaling conventions, and pipelining approaches; 2) presenting the complete design flow and available electronic design and automation tools; 3) developing an encyclopedia of various general and special purpose microprocessors proposed by far; and 4) presenting an evaluation of those works in terms of area on the die and performance metrics. This paper will also serve as guidelines for the asynchronous microprocessor design and implementation in all phases from specification to tape-out.

Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains

In this paper, we introduce a source-synchronous adaptive interface for the globally ratiochronous, locally synchronous design style, a subset of the globally asynchronous, locally synchronous (GALS) design style in which the frequencies of all clocks are not phase-aligned but are constrained to be rationally related, i.e., they are all submultiple of the same physical or virtual frequency. The interface can be designed using only standard cells and guarantees maximal throughput in addition to an average latency four times lower compared with state-of-the-art asynchronous first-input, first-output GALS interfaces. Several properties of the interface are formally stated and proved. We also demonstrate that the interface has a low area overhead, with only four flip-flops per data line, and is robust against nonidealities such as clock jitters and propagation delay misalignments. For a realistic link in 90-nm application-specific integrated circuit technology, we derive a 1-GHz upper bound for the least common multiple among the frequencies.

Automatic adjustment of a medical imaging data acquisition system to unknown delays in the input communication channels

In this article, novel FIFO and RAM-based Synchronization Modules to keep synchronism throughout the input channels of a Data Acquisition Electronics (DAE) system are proposed. DAE is a main component of a Medical Imaging System, namely, a Positron Emission Mammography (PEM) system. DAE input data comes from a scanner constituted by an array of scintillating crystals. The scanner captures radiation generated by human cells injected with a radioactive substance and converts it into electrical signals. The corresponding digital information is sent to the DAE. In order to deal with the huge amount of data, flowing at high data rates, point-to-point (p2p) communication channels are used between the scanner and the DAE. Propagation delays associated with the different communication channels may change differently. Additionally, differences among channel delays may exceed one clock period. Keeping synchronism in these circumstances requires more than the classical asynchronous FIFO solution. All these aspects motivate the work proposed in this article. The PEM DAE system is a multi-board, multi-FPGA, multi-clock domain system. Therefore, the DAE architecture follows a Globally Asynchronous, Locally Synchronous (GALS) design style. The novel Synchronization Modules proposed in this article are implemented in the DAE. The effectiveness of these new structures is validated through simulation and laboratorial test. Simulation and test results are presented.

Is Asynchronous Logic More Robust Than Synchronous Logic?

With clock rates beyond 1 GHz, the model of a system wide synchronous clock is becoming difficult to maintain; therefore, asynchronous design styles are increasingly receiving attention. While the traditional synchronous design style is well-proven and backed up by a rich field experience, comparatively little is known about the properties of asynchronous circuits in practical application. In the face of increased transient fault rates, robustness is a crucial property, and from a conceptual view, the so-called ldquodelay-insensitiverdquo asynchronous design approaches promise to be more robust than synchronous ones, since their operation does not depend on tight timing margins, and data are two-rail coded. A practical assessment of asynchronous designs in fault-injection (FI) studies, however, can rarely be found, and there is a lack of adequate methods and tools in this particular domain. Therefore, the objective of this work is 1) to provide a common approach for efficient and accurate FI in synchronous and in asynchronous designs, and 2) to experimentally compare the robustness of both synchronous and asynchronous designs. To this end, a synchronous 16-bit processor as well as its asynchronous (delay insensitive) equivalent are subjected to signal flips and delay faults. The results of over 489 million experiments are summarized and discussed, and a detailed discussion on the specific properties of the chosen asynchronous design style is given.

Power Management of Voltage/Frequency Island-Based Systems Using Hardware-Based Methods

Shrinking technology nodes combined with the need for higher clock speeds have made it increasingly difficult to distribute a single global clock across a chip while meeting the power requirements of the design. Globally asynchronous locally synchronous (GALS) design style can help achieve low power consumption and modularity of a design while greatly reducing the number of global interconnects. Such multiple clock domain architectures can benefit from having frequency/voltage values assigned to each domain based on workload requirements. The work presented in this paper proposes a new <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">hardware-based</i> approach to dynamically change the frequencies and potentially voltages of a voltage-frequency island (VFI) system driven by a dynamic workload. This technique tries to change the frequency of a synchronous island such that it will have efficient power utilization while satisfying performance constraints. In recent years, there have been major developments, both in industry and academia, in the field of multiprocessor systems. Such multiprocessor systems are very good candidates for VFI design style implementation, where one or more processors can be part of a single VFI. To demonstrate the feasibility of our proposed method, we have implemented a multiprocessor system for a field-programmable gate array (FPGA) platform that uses independently generated clocks for each processor. The results from the FPGA platform confirm the claim that the power consumption of a system can potentially be reduced while maintaining the performance of many applications. Our work concentrates primarily on embedded systems, but the idea can be explored for general-purpose computing as well.

Asynchronous Multiple-Issue On-Chip Bus with In-Order/Out-of-Order Completion

A multiple-issue on-chip bus of a layered architecture in a Globally Asynchronous Locally Synchronous (GALS) design style, supporting in-order/out-of-order completion, is proposed in this letter. The throughput of the proposed on-chip bus is increased by 31.3% and 34.3%. while power consumption overhead is only 6.76% and 3.98%, respectively. as compared to an asynchronous single-issue on-chip bus.

Scan Test Strategy for Asynchronous-Synchronous Interfaces

In the coming years, the well-known synchronous design style will not be able to keep pace with the increase speed and capabilities of integration of advanced processes. New design paradigms, like core reuse of the already designed synchronous modules and asynchronous designs, are considered in order to cope with the ever increasing complexity. The future SoCs will contain multiple synchronous and asynchronous cores. Asynchronous design will become more and more common among digital designers, while synchronous-asynchronous interactions will emerge as a key issue in the future SoC designs. This paper will present test strategies for 2-phase asynchronous-synchronous interfaces and vice versa. It will be shown how test vectors can be automatically generated using commercially available ATPG tools. The generated ATPG vectors will be able to test all stuck-at-faults within the asynchronous-synchronous interfaces.

Globally updated mesochronous design style

In large-scale and high-speed digital systems, global synchronization has frequently been used to protect clocked I/O from data failure due to metastability. Synchronous design styles are widely used, easy to grasp and to implement, and also well supported by logic synthesis tools. There are many drawbacks with global synchronization. Most important is the relationship between physical size and maximum clock frequency, which will approach its limit as clock frequency and system size increase simultaneously. The purpose of this proposed Globally Updated Mesochronous (GUM) design style is to overcome those drawbacks by identifying all global signal links in the system and adding synchronization circuits to these. System level simplicity, inherited from synchronous design and its tool support, is retained. In this paper, the GUM design style is described, analyzed, and demonstrated. Experimental results from a large-scale high-speed system using three 0.8-/spl mu/m BiCMOS chips are given. The GUM design style is scaleable and suitable for future system-on-chip applications both on and among chips.

Automated Synthesis of Mixed-Mode (Asynchronous and Synchronous) Systems

Many large scale integrated circuits and systems contain both synchronous and asynchronous subsystems (including self-timed subsystems). Examples include systems having asynchronous interfaces to busses or memories, and systems containing modules clocked by independent, locally generated clocks. This paper discusses specification and automated synthesis techniques for designing such systems. A graphical perspective of the temporal and interface constraints is provided via a timing diagram editor. The specification and synthesis techniques presented allow individual process implementations to be either synchronous, asynchronous, or combinational. We discuss factors influencing the decomposition of the overall system into sub-processes and the choice of implementation styles. Fragments of the design of a Processor Interface Board (PIB) are used to illustrate various concepts. The goal is to enable a designer to improve design quality by synergistically exploiting the advantages of both the synchronous and asynchronous design styles in a system, and to support experimentation with trade-offs in granularity and implementation strategies.