Symmetric Switching Functions Research Articles

Utilization of Symmetric Switching Functions in the Symbolic Reliability Analysis of Multi-State k-out-of-n Systems

Symmetric switching functions (SSFs) play a prominent role in the reliability analysis of a binary k-out-of-n: G system, which is a dichotomous system that is successful if and only if at least k out of its n components are successful. The aim of this paper is to extend the utility of SSFs to the reliability analysis of a multi-state k-out-of-n: G system, which is a multi-state system whose multi-valued success is greater than or equal to a certain value j (lying between 1 (the lowest output level) and M (the highest output level)) whenever at least km components are in state m or above for all m such that 1 ≤ m ≤ j. This paper is devoted to the analysis of non-repairable multi-state k-out-of-n: G systems with independent non-identical components. The paper utilizes algebraic techniques of multiple-valued logic (together with known properties of SSFs) to evaluate each of the multiple levels of the system output as an individual binary or propositional function of the system multi-valued inputs. The formula of each of these levels is then written as a probability–ready expression, thereby allowing its immediate conversion, on a one-to-one basis, into a probability or expected value. The symbolic reliability analysis of a commodity-supply system (which serves as a standard gold example of a multi-state k-out-of-n: G system) is completed successfully herein, yielding results that have been checked symbolically, and also were shown to agree numerically with those obtained earlier.

Switching-Algebraic Analysis of Multi-State System Reliability

Multi-State systems are systems whose outputs are multi-valued (due to multiple levels of capacity or performance) and (possibly) whose inputs are also multi-valued (due to multiple performance levels or multiple modes of failure). These systems are a generalization of binary or dichotomous systems that have binary or two-valued outputs and inputs. The multi-state reliability model generalizes and adapts many of the concepts and techniques of the binary reliability model, and naturally ends up with sophisticated concepts and techniques of its own. This paper explores the possibility of simply analyzing a multi-state system by reformulating or encoding its inputs in terms of binary inputs and evaluating each of its multiple output levels as an individual binary output of these alternative inputs. This means that we dispense with multiple-valued logic in the analysis of a multi-state system, since this system is now analyzed solely via switching algebra (two-valued Boolean algebra). The wealth of tools and techniques of switching algebra are now used (without any modification or adaptation) in the analysis of the multi-state system (at the cost of an expanded input domain). The paper makes its point though the analysis of a standard commodity-supply system, whose multi-valued inputs are expressed in terms of physically-meaningfully binary inputs. The analysis is made possible through the use of advanced techniques for deriving probability–ready expressions together with the employment of large-size Karnaugh maps and utilization of multiplication tables, symmetric switching functions, and Boolean quotients. Though the system studied involves twelve binary input variables, its manual analysis is completed successfully herein, yielding results that exactly agree with those obtained earlier via automated methods, and are possibly less prone to the notorious effects of round-off errors.

Generating minimal covers of symmetric functions

An algorithm is offered for generating minimum-cost, two-level expressions for totally symmetric, complete switching functions. The algorithms discussed were programmed in TurboPascal (and TurboC) and executed on an IBM PS/2-80. Many symmetric switching functions of from 7 to 15 variables were minimized and the results validated against the original specifications of the functions. Run times varied from a tenth to tens of seconds and were heavily dependent on the size of the input array and the literals of symmetry. >

Multilevel logic synthesis of symmetric switching functions

Designs of totally symmetric functions provided by logic synthesis systems have on average more than twice as many literals as best designs, while the designs of nonsymmetric functions have on average 20% more literals. A simple, but effective, heuristic method for synthesizing symmetric functions that detects and takes advantage of symmetry and is based on classic disjoint decomposition theory is fully developed from basic definitions. Functions are realized as Boolean networks with cost measured as the literal count of factored expressions. Programs based on the method almost always produce the best designs known to the authors. Two strategies for accepting decompositions are explored. They do produce different results in a few cases: examples are presented to show that neither always produces best designs. These programs are proposed as preprocessors for a comprehensive synthesis system. >

Utilization of symmetric switching functions in the computation of k-out-of-n system reliability

Properties of symmetric switching functions are utilized in the development of an algorithm that computes the reliability or unreliability of a k-out-of-n system involving non-identical components. Round-off errors introduced in the computations are analyzed. The algorithm is compared to existing algorithms, and is shown to be of minimal computational complexity. As a bonus, all the intermediate results of the algorithm are meaningful numbers that can facilitate the economic assessment of redundancy.

Symmetric Minimal Covering Problem and Minimal PLA's with Symmetric Variables

This paper first discusses the symmetric property of the minimal covering problem in terms of group theory and then the use of this property in the branch-and-bound method for solving the problem. Computational results on solving sample problems are shown to demonstrate the improvement of computational efficiency of the branch-and-bound method by the utilization of the symmetric property. The sample problems contain the minimal sum derivation of symmetric switching functions, as an application to the design of minimal programmable logic arrays (PLA's). It is shown that when the minimal covering problem derived for the given switching function has symmetric permutations, the given switching function may not be symmetric; although when the given switching function is symmetric, the minimum covering problem obtained from the function is symmetric. The branch-and-bound method based on the symmetric property can be applied not only to symmetric switching functions but also to switching functions which are not symmetric, if the corresponding minimal covering problems have symmetric permutations. The method can be also applied to minimal covering problems which arise outside the minimal sum derivation problems for switching functions.

Magnetic bubble logic

Although the literature on the bubble logic devices is limited, the concepts and device configurations are diverse. In conductor-access devices, logic can be performed by bubble transfer operations. In field-access devices, logic can be performed by providing alternative paths which are selected by interaction between bubbles. Examples include the conjugate logic gates, the resident-bubble cellular logic, and the chevron 3-3 circuits. Logic can also be performed by counting bubbles, such as in the symmetric switching function implementation. The various mechanisms for implementing bubble logic are all described by truth tables. To assess their efficiency, they are compared in terms of space and delay when they are used to implement the same logic element - a full adder. They are all comparable except for the resident-bubble cellular logic which requires excessive space and delay. However, it is important to point out that only the symmetric switching function devices offer rewrite-ability to eliminate the part number problem, and accommodation for a large number of inputs to ease interconnection and delay equalization problems.

On Symmetric Functions with Redundant Variables–Weighted Functions

Any switching function may be transformed into a completely symmetric switching function with some of its variables repetitive. In this paper we shall discuss certain properties, easily detectable in decomposition charts, that may be applied to reduce the number of repeated variables when such a transformation is performed. An algorithm utilizing lookup tables based on these properties has been devised enabling us with relative ease to transform an arbitrary switching function of four variables into a completely symmetric switching function with the least number of variables. The algorithm may be generalized to n-variable switching functions provided that the corresponding lookup tables are made available.

Efficient Exercising of Switching Elements in Nets of Identical Gates

The problem of finding a minimum number of patterns to exercise the logic elements of a combinational switching net is investigated. Throughout, the word “testing” refers to exercising of this kind; or, equivalently, to fault diagnosis where each line of the net can be directly observed. Any set of permanent faults can be selected to test against, examples of which range from “stuck-at” faults (allowing the most economical test) to “any possible fault” (requiring the most complete test). The method used depends upon exact structural analysis rather than upon search algorithms or random pattern generation. The types of results presented appear to be fundamentally new. In particular, the maximum number of patterns required to test any one of an infinite class of nets is frequently found to be finite and extremely small. For example, any nontrivial connected tree of 2-input nand gates can be tested for “any possible fault” by exactly five patterns—no more and no less. The method in brief: Given a set F of switching functions and a set of required inputs for each (collectively denoted T ), a “testing” function is defined for each element of F for each positive integer r . If the lines of a net can be mapped to the domain of the testing functions P ( T, r ) so that the gates perform consistent with these functions, we say the net “accepts” P ( T, r )—and then r patterns are sufficient to test the net for T . Only nets in which each logic element is intended to realize the same switching function are discussed here. Trees (nets without fanout) are studied first, and the conditions under which a tree of identical gates “accepts” a partial function on an arbitrary domain is established. Then the common symmetric switching functions are separately investigated to find for each a minimum value of r such that all trees composed solely of the function accept P ( T, r ) (for various T ). In most cases, as in the example given, the number of patterns required to test any such tree is extremely low. The conditions under which all nets (nontrees included) accept a set of partial functions with arbitrary domain are then established. These conditions are rarely met in practice, even where F consists of a single function. However, many subclasses of nets can be identified which require only a few patterns at most (depending on the function and the class of faults selected). These subclasses often contain nets of arbitrary size and complexity, and frequently consist of exactly those nets for which a related graph can be “colored” (i.e., h -node colored for some particular h ) in the classical graph-theoretic sense. For example, any net of 2-input nand gates can be tested by five patterns if one of its related graphs is 2-colorable and another one is 3-colorable (!). The detailed results and methods used to obtain them are summarized, and in conclusion coloring problems and test construction are commented upon.

An Iterative Technique for Determining the Minimal Number of Variables for a Totally Symmetric Function with Repeated Variables

Several analytic procedures exist for transforming a partially symmetric switching function to a totally symmetric switching function by judiciously repeating certain variables. Presumably the best totally symmetric representation for a given function would be the one having the fewest variables. This note presents an iterative technique for finding the totally symmetric realization for a given function that has the absolute minimum number of variables.

On Multivalued Symmetric Functions

This note describes an algorithm for identifying multivalued symmetric switching functions using parallel processing. Some general properties of multivalued symmetric functions have been investigated. The mixed multivalued symmetric switching function is defined and an algorithm for identifying it is also presented.

Multiform total symmetry and parity functions

In recent letters, Biswas reported the existence of a special class of totally symmetric switching functions which remain invariant for all combinations of complemented and uncomplemented variables of symmetry, and also studied some of their properties. It is shown in this letter that these special symmetric functions are a particular class of linear functions known in literature as odd-parity functions and even-parity functions and form a subclass of totally symmetric functions showing multiform symmetry. Some of the relevant properties of these functions from the viewpoint of linear functions are also studied.

Transformation of Ternary Switching Functions to Completely Symmetric Ternary Switching Functions

It is shown that any ternary switching function can be transformed to a completely symmetric ternary switching function in which some of the variables are repeated. The partial symmetry information inherent in a given function plays a key role in this transformation.

Further Comments on "Synthesis of Symmetric Switching Functions Using Threshold Logic Networks"1

Recently, Fischler and Tannenbaum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> indicated a counter example to Theorem 2 of this author's short note. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> Theorem 2 (as well as the other theorems in the note) is a statement of the sufficiency conditions only. This means that if the conditions given in Theorem 2 are satisfied, then it is always possible to find a minimal realization for five positive transitions. It does not say that if the conditions given in Theorem 2 are not fulfilled, it is not possible to obtain such a network. The counterexample is such a case. The author regrets the use of the phrase "necessary and sufficient conditions" in the abstract and elsewhere in the note. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> This should be read as "sufficient conditions only."

Transformation of Switching Functions to Completely Symmetric Switching Functions

Abstract—A number of techniques exist for realizing completely symmetric switching functions.1 Completely symmetric switching functions are particularly simple and economical to realize using contact-type gating elements. This paper shows that any switching function can be transformed to a completely symmetric switching function in which some of the arguments are redundant. (Obviously, if a given function is already completely symmetric no transformation is necessary.) The partial symmetry information inherent in a given function plays an important role in the transformation. Efficient machine-oriented methods exist for detecting the partial symmetries present in a switching function.

Assumptions in the Threshold Synthesis of Symmetric Switching Functions

Abstract—This note establishes the fact that an optimal synthesis technique (even for a small number of variables) must abandon the basic assumption of assigning only +1 weights to the primary inputs. Examples are presented where both negative primary weights and/or nonunitary primary weights are required to achieve minimality. A method of network analysis is presented which leads to optimal synthesis in a significant number of new cases. The previously accepted lower bound on the number of devices needed to realize a symmetric function is questioned, and a proof is given to establish its validity. A previously published assertion about a least upper bound on the number of devices is shown to be incorrect.

Symmetric Ternary Switching Functions: Their Detection and Realization with Threshold Logic

A simple, systematic procedure for detecting symmetric ternary switching functions is developed. The detection procedure is essentially based on a derived counting theorem. Other important properties and close bounds on the number of ternary symmetric functions are developed. A design method is given whereby symmetric functions can be readily synthesized with switching networks which are economical, and, in certain instances, minimal in the number of ternary threshold devices required. The greatest lower bound on the number of devices required for a given symmetric function is developed.

Feed-Forward Threshold Logic Nets for Digital Switching and Pattern Recognition

A computer-programmable algorithm is presented for the design of general feed-forward nets of threshold logic gates, which realize arbitrary digital switching functions. The algorithm is proved to be convergent for all switching functions. A simplified version of the algorithm is presented for the case of symmetric switching functions. Both algorithms are proved minimal for single-gate nets; a necessary condition is given for the symmetric algorithm to produce minimal two-gate nets when they exist; and two-gate minimality is also demonstrated for the general algorithm, for a certain class of two-gate switching functions. However, general minimality is not proved. The case of partially defined switching functions is treated. Minor alterations in the general algorithm allow its use as an adaptive pattern recognition procedure, where the input variables represent real numbers rather than Boolean variables. Experimental restults are presented for both digital switching-function realization and analog pattern recognition.

Synthesis of Symmetric Switching Functions Using Threshold Logic Elements

The problem of minimal multilevel synthesis of symmetric switching functions with threshold logic elements is studied. A weight matrix representation of a threshold logic network is given. A number of theorems are presented which give necessary and sufficient conditions for minimal synthesis of symmetric functions with a maximum of eight positive transitions. In each case the minimal network is specified. An example has been worked out.

Symmetric Ternary Switching Functions

This paper develops a theory of symmetric ternary switching functions and presents systematic methods for their detection, identification and synthesis. Shannon's theory of binary symmetric functions is extended to ternary functions by defining a set of five ``priming'' operations which, together with the ``permutation'' operations, form a group. Algebraic characterizations of totally and partially symmetric ternary functions are discussed. The method of detection and identification is based on a set of simple rules derived in terms of equalities of the residual functions of the given function with respect to pairs of variables of symmetry in a cyclic order. The notions of fundamental and simple symmetric ternary functions have been introduced and their algebraic properties have been studied. These concepts are then applied to develop a synthesis procedure which uses two basic 3-valued electronic gates recognizing the ``maximum'' or the ``minimum'' of the inputs. Possible generalizations of the results derived in this paper to arbitrarily many-valued functions are indicated.