Symmetric Multiprocessor Architecture Research Articles

Prenaut: Design space exploration for embedded symmetric multiprocessing with various on-chip architectures

Abstract As embedded systems have evolved to appear in many different domains, symmetric multiprocessing (SMP) has been the design choice from low-end to high-end devices. In this paper we present Prenaut, a design space exploration method for finding the best on-chip SMP architectures given processor cores, Level 1, Level 2, and Level 3 caches. Unlike traditional design space exploration tools that are majorly concerned with optimizations in processor, memory and cache structures with a fixed on-chip architecture, Prenaut explores architectures that have not been considered in symmetric multiprocessing domain. These architectures consist of shared instruction caches between cores and heterogeneous cache topologies that feature bypassing a level in the cache hierarchy. The design idea behind Prenaut is to build a data oriented design space exploration method that exploits simulation data to its full extent rather than discarding it. Therefore, Prenaut uses simulation data and applies machine learning methods for estimating design parameters. This provides very rapid estimation of the Pareto set and guides designers through the overall system design process. The design space is pruned by topological clustering of design points which groups similar topologies and new simulation points are selected via an ordered look up table that prevents infeasible random jumps in the design space. For the selected benchmarks, Prenaut can estimate the Pareto set up to 147x faster and the clustering information can reduce the design space up to 82% in comparison with a state-of-the-art evolutionary algorithm.

Design of a Deterministic Service Switch for Avionics Networks

Avionics full-duplex switched Ethernet, with its capability of delivering deterministic latency at low deployment costs, represents a major advance for avionics communication systems. However, avionics full-duplex switched Ethernet does not eliminate contentions at network switches, which may result in an uncontrolled increase in end-to-end latencies, and hence limit the potential of this technology. The use of time to pace packet transmission and forwarding (that is, the adoption of pipeline forwarding) has been demonstrated to avoid contentions at switching nodes in wide-area communication networks, thus being potentially attractive also for avionics networks in general, and avionics full-duplex switched Ethernet in particular. However, questions might arise concerning the actual feasibility of such an approach in the avionics domain due to the possibly high costs required to deploy packet switches able to operate according to a very precise time schedule, which is necessary to respect the stringent delivery deadlines of avionics systems. This paper focuses on the development of a pipeline forwarding switch, showing how simple design guidelines allow a general-purpose symmetric multiprocessor architecture (such as modern personal computers) to offer deterministic and low latency delivery, thus being able to satisfy avionics requirements. The paper also describes a real implementation of a pipeline forwarding switch prototype, based on a dual-processor personal computer and the FreeBSD operating system.

Experimental Evaluation of the Performance of Processing Stealing Technique: A Scalable Load Balancing Technique for a Dynamic Multiprocessor System

paper reports preliminary experimental evaluation of a Processing Elements Stealing (PE-S) technique which was targeted as efficient and scalable load balancing technique for dynamically structured multiprocessor systems. The multiprocessor system is imagined as a dynamic cluster based multiprocessor. Each cluster of the multiprocessor system is a node in symmetric multiprocessor architecture and the number of Processing Element (PE) in each cluster is dynamically determined at runtime. The PE-S technique dynamically computes the configuration ratio using the number of threads in the dynamically assigned tasks to generate the new number of PE for each cluster. This new configuration ratio is thereafter used to balance the additional computational work generated by runtime instantiation of current workloads for each cluster. In this work, the efficiency of the PE-S was evaluated using memory traces of some tightly parallel applications where the amount of parallelism is parameterized. These traces were used as workloads on two different simulation setups; the first is a dynamic multiprocessor with PE-S while the other was also a dynamic multiprocessor but without PE-S. This is to evaluate the performance of the PE-S load balancing technique on the targeted multiprocessor. Also the efficiency of PE-S reconfigurations was compared with other possible reconfiguration ratios. The experimental results showed that the load balancing algorithm is efficient and scalable for balancing at least 100,000 instructions tasks and PE-S generated ratios are averagely better than any other reconfiguration ratios.

Performance of IP-forwarding of Linux hosts with multiple network interfaces

This paper evaluates and compares the performance of IP-packet forwarding of a Linux host equipped with multiple network interface cards (NICs), namely two receiving NICs and one transmitting NIC. We consider a Linux host with SMP (Symmetric Multiprocessing) or multicore multiprocessor (MCMP) architecture. We measure IP forwarding by subjecting an MCMP Linux host to different traffic load conditions of up to 1Gbps. We used the IXIA hardware traffic generator to generate traffic with fixed- and variable-size packets. At the Linux host, generated packets are forwarded/routed from the two receiving NICs to the transmitting NIC. We consider two NIC affinity modes: (I) both receiving NICs are affinitized (or bound) to two cores of the same processor while the transmitting NIC is affinitized to a core on a separate processor, and (II) the transmitting NIC and one receiving NIC are affinitized to two cores of the same processor while the second receving NIC is affinitized to a core on a separate processor. For each affinity mode, we measure the performance for three packet reception mechanisms: NAPI (New API) with a default budget of 300, NAPI with a budget of 2, and Disable and Enable interrupt handling. The performance is measured and compared in terms of various key performance metrics which include throughput, packet loss, round-trip delay, interrupt rates, and CPU availability.

Exploiting parallelism in matrix-computation kernels for symmetric multiprocessor systems

We present a simple and efficient methodology for the development, tuning, and installation of matrix algorithms such as the hybrid Strassen's and Winograd's fast matrix multiply or their combination with the 3M algorithm for complex matrices (i.e., hybrid: a recursive algorithm as Strassen's until a highly tuned BLAS matrix multiplication allows performance advantages). We investigate how modern Symmetric Multiprocessor (SMP) architectures present old and new challenges that can be addressed by the combination of an algorithm design with careful and natural parallelism exploitation at the function level (optimizations) such as function-call parallelism, function percolation, and function software pipelining. We have three contributions: first, we present a performance overview for double- and double-complex-precision matrices for state-of-the-art SMP systems; second, we introduce new algorithm implementations: a variant of the 3M algorithm and two new different schedules of Winograd's matrix multiplication (achieving up to 20% speedup with respect to regular matrix multiplication). About the latter Winograd's algorithms: one is designed to minimize the number of matrix additions and the other to minimize the computation latency of matrix additions; third, we apply software pipelining and threads allocation to all the algorithms and we show how this yields up to 10% further performance improvements.

Using Symmetric Multiprocessor Architectures for High Performance Computing Environments

enhancement for high speed computing can be carried out by using many techniques and architectures at software and high hardware level. Performance enhancement using hardware techniques may include the use of multiple computing nodes or a single node consisting of multiple processors. Symmetric multiprocessor is one of the modern architectures used to perform extensive computations. Symmetric multiprocessors have many configuration modes to carry out these heavy computations. The performance of Symmetric multiprocessors is analyzed and compared with high-fidelity models. Processors models are used to design and construct the architectures of symmetric multiprocessors. In this research paper such kind of critical design aspects of symmetric multi processors have been analyzed for further enhancement of the existing technology.

Parallelisation of Implicit Time Domain Methods: Progress with ADI-FDTD

The parallelisation of implicit time domain solvers is essential for applications requiring large, highly over-sampled meshes that exceed the memory limitations of standalone workstations (1). Prime application examples include large arrays of small antennas (2), and on- chip interconnects for state of the art integrated circuits (IC) (3). The need for highly over sampled meshes in these applications can be illustrated by example. Current on-chip IC interconnect widths can be as low as 22nm or less, yet cover an area > 100(mm) 2 and transmit signals with fundamental frequencies in the range DC-10GHz. Typically, transient efiects involving high frequencies are of the most interest, but even this can still require meshes with ¢x < (‚0=10 6 ), i.e., four to flve orders of magnitude smaller than for typical FDTD meshes (neglecting considerations relating to material properties). It is not practical to use explicit FDTD solvers for such meshes, even in parallel, because the Courant-Friedrichs-Lewy (CFL) stability criteria enforces a commensurate reduction in the time step size for numerical reasons. While implicit FDTD solvers, such as ADI-FDTD, ofier freedom from the CFL stability criteria, it has been presumed that parallel implementations on all but the most specialised architectures (4) would be of little beneflt due to the high communication overhead. However, we have been able to show that this is not the case (5). In this Paper we will present an overview of our work to date on the parallelisation of implicit time domain methods, including parallel ADI-FDTD (1,5) and parallel ADI-BOR-FDTD (6) on both symmetric multiprocessor (SMP) and distributed memory computer clusters (DMCC). We do not parallelise the tri-diagonal matrix solver itself, because each 2D matrix must have more than 4,000 (40,000) elements per direction before this becomes e-cient for SMP (DMCC) ma- chines. This requires 3D domains at are at or beyond current memory limits for state of the art machines. Instead, we employ domain decomposition and solve multiple, smaller, tri-diagonal ma- trix systems in parallel. Carefully organised data exchanges avoid unnecessary double-handling of data during communication, improving the parallel algorithm performance. We will describe our domain decomposition scheme, and show results for small and large domains, comparing par- allel FDTD and parallel ADI-FDTD and parallel BOR-FDTD with parallel ADI-BOR-FDTD. We demonstrate e-cient solutions of large full 3D meshes with 8 billion mesh cells for paral- lel ADI-FDTD. Since machines with SMP and DMCC architectures are widely available, our demonstration of parallel speed up represents an important step forward for the application of implicit time domain solvers for large, highly oversampled meshes with ¢x < 10 i2 ‚. We expect that our parallelisation approach can be adopted for related implicit FDTD methods.

Parallelization methods for implementation of a magnetic induction tomography forward model in symmetric multiprocessor systems

This paper describes four parallelization approaches used in a finite-difference-based electromagnetic modeller for application in magnetic induction tomography (MIT) and suitable for implementation on computer systems with symmetric multiprocessor (SMP) architecture. The approaches include: (i) splitting by coils using a distributed memory approach, (ii) splitting by physical domain using a distributed memory approach, (iii) splitting by physical domain using hybrid distributed/shared memory approach and (iv) splitting by both coils and physical domain using multi-level distributed and shared memory approaches respectively. All four approaches were implemented and tested on an IBM SP supercomputer. Coil parallelization was the most efficient method due to low inter-processor communication requirements but was limited by the number of coils in the MIT system. Approaches (ii) and (iii) allowed a larger number of processors to be employed but the efficiency versus number of processors was found to drop at a faster rate in comparison to (i). The fourth approach both allowed a larger number of processors to be employed and was found to provide higher efficiency than the parallelization by physical domain only. This multi-level hybrid approach therefore appears to offer an effective parallelization method for implementation of the MIT forward model on SMP clusters.

A multiprocessor system-on-chip for real-time biomedical monitoring and analysis

In this article we focus on multiprocessor system-on-chip (MPSoC) architectures for human heart electrocardiogram (ECG) real time analysis as a hardware/software (HW/SW) platform offering an advance relative to state-of-the-art solutions. This is a relevant biomedical application with good potential market, since heart diseases are responsible for the largest number of yearly deaths. Hence, it is a good target for an application-specific system-on-chip (SoC) and HW/SW codesign. We investigate a symmetric multiprocessor architecture based on STMicroelectronics VLIW DSPs that process in real time 12-lead ECG signals. This architecture improves upon state-of-the-art SoC designs for ECG analysis in its ability to analyze the full 12 leads in real time, even with high sampling frequencies, and its ability to detect heart malfunction for the whole ECG signal interval. We explore the design space by considering a number of hardware and software architectural options. Comparing our design with present-day solutions from an SoC and application point-of-view shows that our platform can be used in real time and without failures.

Application-specific heterogeneous multiprocessor synthesis using extensible processors

The complexity of many embedded software applications and their stringent performance requirements have reached a point where they can no longer be supported by conventional embedded-system architectures based on a single general-purpose processor. Nanometer fabrication technologies have made it feasible to integrate several embedded processors on a single chip to create multiprocessor systems-on-chip (MPSoCs) for a wide range of applications. It is already well known that, for embedded systems, customizing the processor to the application can significantly increase performance and energy efficiency. Single-chip heterogeneous multiprocessors, where the different processors are customized to the tasks they perform, are thus attracting attention. Despite their significant potential, a primary bottleneck to their adoption remains the development of programming paradigms and tools to alleviate the design complexity. Some advances have been made in the areas of custom multiprocessor architecture, tool support, and design methodology in order to reduce the design turnaround time. However, because of the heterogeneity of the custom processors, the designers are still required to manually map the application tasks to the different processors and, at the same time, customize each processor so that the overall performance requirements are satisfied. A multilevel custom multiprocessor-synthesis methodology to perform the assignment and scheduling of the application tasks on the various processors together with processor customization in an integrated manner is proposed. This paper focuses on extensible processors, which provide a good tradeoff between efficiency, flexibility, and design turnaround time, by combining a configurable base processor with hardware that implements custom instructions to extend its instruction set. This paper motivates the need for such an integrated approach by demonstrating that custom-instruction selection has complex interdependencies with task assignment and scheduling, and performing these steps independently often results in significant degradation in the quality of the synthesized multiprocessor architecture. The methodology presented here uses an iterative improvement algorithm to first assign and schedule tasks on processors and then select custom instructions along the critical path. It utilizes the concept of "expected execution time" to connect these two steps. It not only considers the currently selected custom instructions for the current task assignment and schedule, but also the possibility of better custom instructions being selected in future iterations. The methodology presented here is also enhanced to integrate task-level software pipelining to further increase the parallelism in the task graph and provide opportunities for multiprocessing. In this paper, the proposed heterogeneous multiprocessor-synthesis methodology is implemented in the context of a commercial extensible-processor design flow, using the Xtensa platform from Tensilica Inc. The presented tool was evaluated by automatically generating custom multiprocessor architectures for several complex embedded software benchmarks. The results show that architectures synthesized by the proposed methodology demonstrate an average speedup of 2.0/spl times/ (up to 2.9/spl times/) compared to symmetric multiprocessor architectures in which the processors have not been augmented with custom instructions. To the best of the authors' knowledge, this is the first tool for the synthesis of custom MPSoCs using extensible processors.

Large-eddy simulations on distributed shared memory clusters

The practicality of Large-eddy simulation (LES) of turbulent combustion, as is found in gas turbine engines, on clusters of commodity PC-based symmetric multi-processor (SMP) systems in 2-, 4-, and 8-way configurations has been investigated. Bandwidth demands from both memory and networking in the benchmark LES algorithm are shown to the primary performance inhibitors. Contention in the various SMP architectures tested is shown to compound these two hardware limitations. To investigate the ability of the parallel clustered systems, low-level hardware studies are conducted in conjunction with bench-marking of the LES application. The hardware tests focus on memory and communication contention under loads found in the LES algorithm. For comparison, the benchmarks are also applied to two industry leading high-performance super-computing architectures. It is found that contention in the 4- and 8-way SMP architecture studied here limits their applicability while the 2-way systems shows competitive performance and speed-up compared to its industry counter-parts. It is concluded that design-level combustion LES on clusters of commodity hardware, when equipped with sufficient memory and communication bandwidth, are a viable substitute for more expensive super-computing platforms.

Shared memory multiprocessor architectures for software ip routers

We propose new shared memory multiprocessor architectures and evaluate their performance for future Internet protocol (IP) routers based on symmetric multiprocessor (SMP) and cache coherent nonuniform memory access (CC-NUMA) paradigms. We also propose a benchmark application suite, RouterBench, which consists of four categories of applications representing key functions on the time-critical path of packet processing in routers. An execution driven simulation environment is created to evaluate SMP and CC-NUMA router architectures using this RouterBench. The execution driven simulation can produce accurate cycle-level execution time prediction and reveal the impact of various architectural parameters on the performance of routers. We port the FUNET trace and its routing table for use in our experiments. We find that the CC-NUMA architecture provides an excellent scalability for design of high-performance IP routers. Results also show that the CC-NUMA architecture can sustain good lookup performance, even at a high frequency of route updates.

Adapting a parallel sparse direct solver to architectures with clusters of SMPs

We consider the direct solution of general sparse linear systems baseds on a multifrontal method. The approach combines partial static scheduling of the task dependency graph during the symbolic factorization and distributed dynamic scheduling during the numerical factorization to balance the work among the processes of a distributed memory computer. We show that to address clusters of Symmetric Multi-Processor (SMP) architectures, and more generally non-uniform memory access multiprocessors, our algorithms for both the static and the dynamic scheduling need to be revisited to take account of the non-uniform cost of communication. The performance analysis on an IBM SP3 with 16 processors per SMP node and up to 128 processors shows that we can significantly reduce both the amount of inter-node communication and the solution time.

Parallel optical interconnects may reduce the communication bottleneck in symmetric multiprocessors

We start with a detailed analysis of the communication issues in today's symmetric multiprocessor (SMP) architectures to study the benefits of implementing optical interconnects (OI) in these machines. We show that the transmission of block addresses is the most critical communication bottleneck of future large SMPs owing to the need to preserve the coherence of data duplicated in caches. An address transmission bandwidth as high as 200-300 Gb/s may be necessary in ten years from now; this requirement will represent a difficult challenge for shared electric buses. In this context we suggest the introduction of simple point-to-point OIs for a SMP cache-coherent switch, i.e., for a VLSI switch that would emulate the shared-bus function. The operation might require as much as 10,000 input-outputs (IOs) to connect 100 processors, particularly if one maintains the present parallelism of transmissions to preserve a large bandwidth and a short memory access latency. The interest for OIs comes from the potential increase of the transmission frequency and from the possible integration of such a high density of IOs on top of electronic chips to overcome packaging issues. Then we consider the implementation of an optical bus that is a multipoint optical line involving more optical technology. This solution allows multiple simultaneous accesses to the bus, but the preservation of the coherence of caches can no longer be maintained with the usual fast snooping protocols.

Prefix Computations on Symmetric Multiprocessors

We introduce a new prefix computation algorithm on linked lists which builds upon the sparse ruling set approach of Reid-Miller and Blelloch. Besides being somewhat simpler and requiring nearly half the number of memory accesses, we can bound our complexity with high probability instead of merely on average. Moreover, whereas Reid-Miller and Blelloch targeted their algorithm for implementation on a vector multiprocessor architecture, we develop our algorithm for implementation on the symmetric multiprocessor architecture (SMP). These symmetric multiprocessors dominate the high-end server market and are currently the primary candidate for constructing large scale multiprocessor systems. Our prefix computation algorithm was implemented in C using POSIX threads and run on four symmetric multiprocessors: the HP-Convex Exemplar (S-Class), the IBM SP-2 (High Node), the SGI Power Challenge, and the DEC AlphaServer. We ran our code using a variety of benchmarks which we identified to examine the dependence of our algorithm on memory access patterns. For some problems, our algorithm actually matched or exceeded the performance of the standard sequential solution using only a single thread. Moreover, in spite of the fact that the processors must compete for access to main memory, our algorithm still achieved scalable performance with up to 16 processors, which was the largest platform available to us.

Server capacity planning for Web traffic workload

The goal of the paper is to provide a methodology for determining bandwidth requirements for various hardware components of a World Wide Web server. The paper assumes a traditional symmetric multiprocessor (SMP) architecture for the Web server, although the same analysis applies to an SMP node in a cluster. The paper derives formulae for bandwidth demands for memory, processor data bus, network adapters, disk adapters, I/O memory paths, and I/O buses. Since the Web workload characteristics vary widely, three sample workloads are considered for illustrative purposes: 1) standard SPECweb96; 2) a SPECweb96-like workload that assumes dynamic data and retransmissions; and 3) WebProxy, which models a Web proxy server that does not do much caching, and thus has rather severe requirements. The results point to a few general conclusions regarding Web workloads. In particular, reduction in memory/data bus bandwidth by using the virtual interface architecture (VIA) is very desirable, and the connectivity needs may go well beyond the capabilities of traditional systems based on the traditional PCI-bus. Web workloads also demand a significantly higher memory bandwidth than data bus bandwidth and this disparity is expected to increase with the use of VIA. Also, the current efforts to offload TCP/IP processing may require a larger headroom in I/O subsystem bandwidth than in the processor-memory subsystem.

Scalable computations in penetration mechanics

This paper presents an overview of an explicit message-passing paradigm for a Eulerian finite volume method for modeling solid dynamics problems involving shock wave propagation, multiple materials, and large deformations. Three-dimensional simulations of high-velocity impact were conducted on the IBM SP2, the SGI Power Challenge Array, and the SGI Origin 2000. The scalability of the message-passing code on distributed-memory and symmetric multiprocessor architectures is presented and compared to the ideal linear performance.