Symmetric Multiprocessor Systems Research Articles

Model Optimization for A Dynamic Rail Transport System on an Asymmetric Multi-Core System

The problem of optimization of the rolling dynamics model is considered. That providing safe movement at high frequency when interacting with the railway. Moreover, allowing to evaluate the dynamic parameters when designing new and modernizing existing locomotives. The object of this research is a rail transport dynamic system model. The article's purpose is to increase the efficiency of the digital hardware in the rolling stock loop model by optimizing the organization of the computing process. The mathematical model analysis of the object made it possible to attribute it to the class of hard real-time systems. The computation of the model phase variables with different frequencies is necessary to optimize the simulation time of the train movements and is performed by splitting the original algorithm into parallel threads. The developed planning algorithm and the cyclic schedule implementation for the model of a dynamic real-time object consider microarchitecture solutions of symmetric multiprocessor systems with shared memory and methods for optimizing software tools. The experiments confirmed the operability of the optimized model. Also, allow us to recommend it for practical use in studying objects and determine the dynamic force of trolley structural elements during operation. Analysis of the optimized model simulation results, using cyclic schedules shows the correspondence of the obtained simulation results to the standard. The main advantage of the model is the increase in productivity when performing data processing by reducing the processor time. The optimized cyclic schedule algorithm of the semi-natural modeling platform is used for the subsequent development of the control system in real and accelerated time scales.

Research on FFT Algorithm Use SMP System

Based on the theoretical research of a series of algorithms of adaptive beamforming and space-time adaptive processing, it is necessary to discuss the implementation of related algorithms on the machine hardware platform. Fast Fourier transform (FFT) is an essential process in this implementation. With the development of array antennas, the number of points to be calculated by the FFT has also increased significantly. Therefore, the ultra-large point FFT has become a key technology for current antenna signal processing. Most of the existing FFT algorithms are researched based on single-core processors, and there is very little literature on the research of super-large-point FFT algorithms suitable for Symmetric Multiprocessor (SMP). In this paper, through analyzing the characteristics of a symmetric multi-processor (SMP) parallel processing system, the very large FFT fast algorithm (VLFFT) is proposed. This algorithm significantly reduces the dependence on memory and improves the FFT's performance using the limited rules of the one-dimensional sequence split, changing the twiddle factor calculation method, and optimizing the data distribution and storage access. And the research's optimized very large FFT algorithms is also summarized in the paper. Experiment results show that the algorithm is suitable for the SMP platform and can effectively solve the problem of the very large FFT, which make single-core processors harder to realize.

Methods to model and simulate super carbon nanotubes of higher order

SummarySuper carbon nanotubes (SCNTs) are of interest in material design because of their strength and weight characteristics. In this paper, we present a graph algebra‐based approach to model and construct SCNTs of arbitrary order. The SCNTs are represented by directed graphs with Y junctions as basic modeling element. A new data structure to store these graphs is proposed that capitalizes on the hierarchy within SCNTs and allows efficient queries for nodes and edges. Symmetry considerations for SCNTs are conducted and related to the graph algebra‐based modeling. We present an extended and improved algorithm for simulating the mechanical behavior of SCNTs. Compared with our previous work on level 0 SCNTs, the performance is improved by a factor higher than 2 when running in serial and a factor up to 4.4 when running in parallel on a 16‐core symmetric multiprocessing system. A new pre‐processing step exploiting structural symmetry and an improved proximity‐aware matrix‐vector‐multiplication routine make this performance improvement possible while only consuming little additional memory. We also now consider SCNTs of order 1 and 2. Experimental results show that our new solver is up to 1.4 times faster than a compressed‐row‐storage based reference solver, on order 0, 1, and 2 SCNTs, with and without deformations, while requiring only half the memory. Because memory is the limiting factor for the feasibility of such simulations, our new approach significantly expands the realm of feasibility for such simulations. Copyright © 2016 John Wiley & Sons, Ltd.

MicMR: An efficient MapReduce framework for CPU–MIC heterogeneous architecture

With the high-speed development of processors, coprocessor-based MapReduce is widely studied. In this paper, we propose micMR, an efficient MapReduce framework for CPU–MIC heterogeneous architecture. micMR mainly provides the following new features. First, the two-level split and the SIMD friendly map are designed for utilizing the Vector Process Units on MIC. Second, heterogeneous pipelined reduce is developed for improving the efficiency of resource utilization. Third, a memory management scheme is designed for accessing <key, value> pairs in both the host and the MIC memory efficiently. In addition, optimization techniques, including load balancing, SIMD hash, and asynchronous task transfer, are designed for achieving more speedups. We have developed micMR not only in a single node with CPU and MIC but also in a CPU–MIC heterogeneous cluster. The experimental results show that micMR is up to 8.4x and 45.8x faster than Phoenix++, a high-performance MapReduce system for symmetric multiprocessing system, and up to 2.0x and 5.1x faster than Hadoop in a CPU–MIC cluster.

The Effect of NUMA Tunings on CPU Performance

Non-Uniform Memory Access (NUMA) is a memory architecture for symmetric multiprocessing (SMP) systems where each processor is directly connected to separate memory. Indirect access to other CPU's (remote) RAM is still possible, but such requests are slower as they must also pass through that memory's controlling CPU. In concert with a NUMA-aware operating system, the NUMA hardware architecture can help eliminate the memory performance reductions generally seen in SMP systems when multiple processors simultaneously attempt to access memory.The x86 CPU architecture has supported NUMA for a number of years. Modern operating systems such as Linux support NUMA-aware scheduling, where the OS attempts to schedule a process to the CPU directly attached to the majority of its RAM. In Linux, it is possible to further manually tune the NUMA subsystem using the numactl utility. With the release of Red Hat Enterprise Linux (RHEL) 6.3, the numad daemon became available in this distribution. This daemon monitors a system's NUMA topology and utilization, and automatically makes adjustments to optimize locality.As the number of cores in x86 servers continues to grow, efficient NUMA mappings of processes to CPUs/memory will become increasingly important. This paper gives a brief overview of NUMA, and discusses the effects of manual tunings and numad on the performance of the HEPSPEC06 benchmark, and ATLAS software.

A High-Performance Double-Layer Counting Bloom Filter for Multicore Systems

The snoopy-based protocol is a widely used cache coherence mechanism for a symmetric multiprocessor (SMP) system. However, this broadcast-based protocol blindly disseminates data sharing information across the system, and introduces many unnecessary data operations. This paper proposes a novel architecture of double-layer counting Bloom filter (DLCBF) to reduce the unnecessary data lookups on the local cache and redundant data transactions on the shared interconnection of an SMP system. By adding an extra filtering layer, the DLCBF effectively exploits the data locality of applications. The two-layer hierarchy reduces the storage size of DLCBF by 18.75%, and achieves 81.99% and 31.36% better filtering rates when compared with a classic Bloom filter (BF) and original counting BF, respectively. When applied on the segmented shared bus of an SMP system, the DLCBF outperforms the previous work by 58% for In-filters and $1.86\times $ for Out-filters. This paper also comprehensively explores the key design parameters of DLCBF, including the sizes of top-layer, bottom-layer, and multilayer design. The results show that enlarging the layer filters enhance the filtering rates of DLCBF, while adding an extra filter layer only provides slight benefit.

On-Line Dynamic Voltage Scaling for EDZL Scheduling on Symmetric Multiprocessor Real-Time Systems

EDZL (Earliest Deadline Zero Laxity) scheduling is known to be at least as EDF (Earliest Deadline First) in task scheduling on symmetric multiprocessor real-time systems; however, there are few works on energy conversation on the EDZL. This paper proposes an on-line Dynamic Voltage Scaling (DVS) algorithm of the global EDZL to reduce energy consumption of real-time tasks. The proposed algorithm dynamically adjusts processor speed at each scheduling point with re-assigning deadlines of active jobs that reduces power consumption of processors while making all real-time tasks schedulable by EDZL. Extensive simulations show that the proposed algorithm reduces power consumption more than the previous algorithm for EDZL.

Distributed Seams for Gigapixel Panoramas

Gigapixel panoramas are an increasingly popular digital image application. They are often created as a mosaic of many smaller images. The mosaic acquisition can take many hours causing the individual images to differ in exposure and lighting conditions. A blending operation is often necessary to give the appearance of a seamless image. The blending quality depends on the magnitude of discontinuity along the image boundaries. Often, new boundaries, or seams, are first computed that minimize this transition. Current techniques based on multi-labeling Graph Cuts are too slow and memory intensive for gigapixel sized panoramas. In this paper, we present a parallel, out-of-core seam computing technique that is fast, has small memory footprint, and is capable of running efficiently on different types of parallel systems. Its maximum memory usage is configurable, in the form of a cache, which can improve performance by reducing redundant disk I/O and computations. It shows near-perfect scaling on symmetric multiprocessing systems and good scaling on clusters and distributed shared memory systems. Our technique improves the time required to compute seams for gigapixel imagery from many hours (or even days) to just a few minutes, while still producing boundaries with energy that is on-par with Graph Cuts.

A dual speed scheme for dynamic voltage scaling on real-time multiprocessor systems

This paper proposes an off-line dynamic voltage scaling (DVS) scheme that can be integrated with EDF$$^{(k)}$$(k), which is a global real-time scheduling algorithm for symmetric multiprocessor systems. The scheme computes the static execution speed for each individual task assuming the task's worst-case execution. Based on the individual speed, it determines static dual speeds off-line for each task to make use of the gap between actual execution demand and the worst-case execution demand. The simulation results show that the proposed scheme combined with an existing online DVS technique can reduce energy consumption by up to 37 % compared with a uniform speed technique when the number of processors is 32.

A parallel strategy and performance analysis of the EM-like reconstruction method for diffuse optical tomography

The EM-like reconstruction method for steady state diffuse optical tomography is a propagation back-propagation method and its sequential implementation requires excessively longer computation time. Hence we apply a parallel strategy to the reconstruction method. We divide the groups of boundary measurements into several nonoverlapping subsets and each subset of boundary measurements are handled by selected processing element. We take two-dimensional numerical experiments on a single Symmetric Multi-Processing system to test the performance of the parallel strategy. The computation time of the parallel implementation indicates that high performance of computation can be obtained. Besides, the more groups of boundary measurements are used for the reconstruction, the higher speed-up and parallel efficiency can be achieved. Due to the usage of memory, the curve of speed-up with respect to different numbers of processing elements appears a wave pattern while the curve of efficiency with respect to different numbers of processing elements decreases rapidly. Thus, for three-dimensional reconstruction problem, we can execute the parallel reconstruction scheme on a cluster which aligns multiple workstations by a network.

Symmetric Multi-Processing 시스템에서 다양한 병렬 기법 모델을 적용한 병렬 CUPID 코드의 성능분석

A parallelization of the bi-conjugate gradient solver for the pressure equation of the CUPID (component unstructured program for interfacial dynamics) code, which was developed for analyzing the components of a pressurized water-cooled reactor, was studied in a symmetric multi-processing system. The parallel performance was investigated for three typical parallel programming models (MPI, OpenMP, Hybrid) by solving incompressible backward-facing step flow at various grid resolutions. It was confirmed that parallel performance was low when problem size was small or the memory requirement for each thread was considerably higher than the cache memory. Furthermore, it was shown that MPI was better than OpenMP regardless of the problem size, and Hybrid was the best when the number of threads was relatively small.

Analytical Method of Performance Prediction in Parallel Algorithms

With the availability of powerful personal computers, workstations and networking devices, the recent trend in parallel computing is to connect a number of individual workstations (PC, PC SMP) to solve computation-intensive tasks in parallel way on such typical clusters as NOW, SMP, Grid). In this sense it is not more true to consider traditionally evolved parallel computing and distributed computing as two separate research disciplines. Current trends in high performance computing (HPC) are to use networks of workstations (NOW, SMP) as a cheaper alternative to traditionally used massively parallel multiprocessors or supercomputers and to profit from unifying of both mentioned disciplines. The individual workstations could be so single PC (Personal computer) as parallel computers based on modern symmetric multiprocessor systems (SMP) implemented within workstation. To exploit the parallel processing capability of such cluster, the application program must be paralleled. The effective way to do it for (parallelisation strategy) belongs to a most important step in developing effective parallel algorithm (optimisation). For behaviour analysis we have to take into account all overheads that have the influence to performance of parallel algorithms (architecture, computation, communication etc.). In this article we discuss such complex performance evaluation of abstract empty matrix for potential used decomposition strategies. For these decomposition strategies we derived analytical isoefficiency functions, which allow us to predict performance although for hypothetical parallel computer.

Analysis and implementation of the multiprocessor bandwidth inheritance protocol

The Multiprocessor Bandwidth Inheritance (M-BWI) protocol is an extension of the Bandwidth Inheritance (BWI) protocol for symmetric multiprocessor systems. Similar to Priority Inheritance, M-BWI lets a task that has locked a resource execute in the resource reservations of the blocked tasks, thus reducing their blocking time. The protocol is particularly suitable for open systems where different kinds of tasks dynamically arrive and leave, because it guarantees temporal isolation among independent subsets of tasks without requiring any information on their temporal parameters. Additionally, if the temporal parameters of the interacting tasks are known, it is possible to compute an upper bound to the interference suffered by a task due to other interacting tasks. Thus, it is possible to provide timing guarantees for a subset of interacting hard real-time tasks. Finally, the M-BWI protocol is neutral to the underlying scheduling policy: it can be implemented in global, clustered and semi-partitioned scheduling. After introducing the M-BWI protocol, in this paper we formally prove its isolation properties, and propose an algorithm to compute an upper bound to the interference suffered by a task. Then, we describe our implementation of the protocol for the LITMUS RT real-time testbed, and measure its overhead. Finally, we compare M-BWI against FMLP and OMLP, two other protocols for resource sharing in multiprocessor systems.

Exploiting parallelism in matrix-computation kernels for symmetric multiprocessor systems

We present a simple and efficient methodology for the development, tuning, and installation of matrix algorithms such as the hybrid Strassen's and Winograd's fast matrix multiply or their combination with the 3M algorithm for complex matrices (i.e., hybrid: a recursive algorithm as Strassen's until a highly tuned BLAS matrix multiplication allows performance advantages). We investigate how modern Symmetric Multiprocessor (SMP) architectures present old and new challenges that can be addressed by the combination of an algorithm design with careful and natural parallelism exploitation at the function level (optimizations) such as function-call parallelism, function percolation, and function software pipelining. We have three contributions: first, we present a performance overview for double- and double-complex-precision matrices for state-of-the-art SMP systems; second, we introduce new algorithm implementations: a variant of the 3M algorithm and two new different schedules of Winograd's matrix multiplication (achieving up to 20% speedup with respect to regular matrix multiplication). About the latter Winograd's algorithms: one is designed to minimize the number of matrix additions and the other to minimize the computation latency of matrix additions; third, we apply software pipelining and threads allocation to all the algorithms and we show how this yields up to 10% further performance improvements.

Optimizations and OpenMP implementation for the direct simulation Monte Carlo method

Parallel implementation of a three-dimensional direct simulation Monte Carlo (DSMC) code employing complex data structures and dynamic memory allocation is detailed for shared memory systems using Open Multi-Processing (OpenMP). Several techniques to optimize the serial implementation of the DSMC method are first discussed. Specifically for a 3-level Cartesian grid, a Cartesian-based movement technique including particle indexing is demonstrated to result in a modest decrease in overall simulation expense of 34% compared with a ray-tracing technique combined with stored cell-connectivity. Two strategies for data localization leading to optimal usage of cache memory are demonstrated to speed up certain cell-based functions (such as collision computations) by a factor of 3.38–4.36. The shared-memory parallel implementation using OpenMP is then described in detail. Synchronization points and related critical sections are identified as major factors that impact the OpenMP parallel performance. Techniques to remove all such synchronization points in the OpenMP implementation of the DSMC method are outlined. For dual-core and quad-core systems, speedups of 1.99 and 3.74, respectively, are obtained for a (free-stream flow) test simulation with low granularity. Finally, the parallel performance of identical source code employing OpenMP is shown to be strongly correlated to the underlying computer architecture. Both Symmetric Multiprocessor (SMP) and non-uniform memory access (NUMA) systems are studied in order to achieve a better understanding of their impacts on parallel scalability when using OpenMP.

Micromagnetic Analysis of Shielded Write Heads Using Symmetric Multiprocessing Systems

Acceleration of micromagnetic calculations on symmetric multiprocessing (SMP) systems is investigated. A speed up of more than 20 times has been realized compared with the serial processing software. The SMP system with the optimized software has a speed up of 5.6 times compared to a previous version on an 8-CPU cluster system. Micromagnetic analysis of a write head with trailing and side shields is performed to derive the quasi-static recording field distributions, dynamic recording fields and magnetization rotation processes. It is noted that the dynamic recording field is affected by the trailing and side shields. A write head for shingled recording is also analyzed and is found to be promising due to its higher recording field.

Fuzzy expert system for load balancing in symmetric multiprocessor systems

The aim of this paper is to describe a fuzzy expert system for load balancing in a symmetric multiprocessor environment. Load balancing algorithms are used to share the load of the system fairly among the processors. The developed load balancing algorithm use on demand based approach instead of the periodic load balancing in order to get fast and fair load balancing with minimal computational overhead. It uses the number of threads per processor and total load of the system as inputs. The method is compared to the periodic and another developed on demand based algorithms. The results show that during the load balancing the periodic algorithm causes temporary idle periods in the processors whereas the developed on demand-based algorithms respond faster to the fluctuating load level, stabilize the load more equally among the processors and increase the performance of the system. The results also proof that the fuzzy load balancer achieves the best load balance among the processors as well as the fastest response time.

Performance evaluation of iterative parallel algorithms

PurposeWith the availability of powerful personal computers (PCs), workstations and networking devices, the recent trend in parallel computing is to connect a number of individual workstations (PC and PC symmetric multiprocessor systems (SMP)) to solve computation‐intensive tasks in parallel way on such clusters (networks of workstations (NOW), SMP and Grid). In this sense, it is not more true to consider traditionally evolved parallel computing and distributed computing as two separate research disciplines. Current trends in high performance computing are to use NOW (and SMP) as a cheaper alternative to traditionally used massively parallel multiprocessors or supercomputers and to profit from unifying of both mentioned disciplines. The purpose of this paper is to consider the individual workstations could be so single PC as parallel computers based on modern SMP implemented within workstation.Design/methodology/approachSuch parallel systems (NOW and SMP), are connected through widely used communication standard networks and co‐operate to solve one large problem. Each workstation is threatened similarly to a processing element as in a conventional multiprocessor system. But, personal processors or multiprocessors as workstations are far more powerful and flexible than the processing elements in conventional multiprocessors. To make the whole system appear to the applications as a single parallel computing engine (a virtual parallel system), run‐time environments such as OpenMP, Java (SMP), message passing interface, Java (NOW) are used to provide an extra layer of abstraction.FindingsTo exploit the parallel processing capability of such cluster, the application program must be paralleled. The effective way how to do it for (parallelisation strategy) belongs to a most important step in developing effective parallel algorithm (optimisation). To behaviour analysis, all overheads that have the influence to performance of parallel algorithms (architecture, computation, communication, etc.) have to be taken into account. In this paper, such complex performance evaluation of iterative parallel algorithms (IPA) and their practical implementations are discussed (Jacobi and Gauss‐Seidel iteration). On real application example, the various influences in process of modelling and performance evaluation and the consequences of their distributed parallel implementations are demonstrated.Originality/valueThe paper usefully shows that better load balancing can be achieved among used network nodes (performance optimisation of parallel algorithm). Generally, it claims that the parallel algorithms or their parts (processes) with more communication (similar to analyzed Gauss‐Seidel parallel algorithm) will have better speed‐up values using modern SMP parallel system as its parallel implementation in NOW. For the algorithms or processes with small communication overheads (similar to analysed Jacobi parallel algorithm) the other network nodes can be used based on single processors.

IBM System z10 processor cache subsystem microarchitecture

With the introduction of the high-frequency IBM System z10™ processor design, a new, robust cache hierarchy was needed to enable up to 80 of these processors aggregated into a tightly coupled symmetric multiprocessor (SMP) system to reach their performance potential. Typically, each time the processor frequency increases by a significant factor, as did the z10™ processor over the predecessor IBM System z9® processor, the access time of data, as measured by the number of processor cycles beyond the level 1 cache on an identical processor cache subsystem, would increase proportionally as well because the flight time on the chip interconnects across multiple hardware packaging levels has stayed relatively constant in nanoseconds. To address the latency scaling problem and the increased demand of the larger 80-way SMP size, the z10 processor cache subsystem introduces new innovative concepts and solutions.

High Performance Inverse Preconditioning

The derivation of parallel numerical algorithms for solving sparse linear systems on modern computer systems and software platforms has attracted the attention of many researchers over the years. In this paper we present an overview on the design issues of parallel approximate inverse matrix algorithms, based on an anti-diagonal “wave pattern” approach and a “fish-bone” computational procedure, for computing explicitly various families of exact and approximate inverses for solving sparse linear systems. Parallel preconditioned conjugate gradient-type schemes in conjunction with parallel approximate inverses are presented for the efficient solution of sparse linear systems. Applications of the proposed parallel methods by solving characteristic sparse linear systems on symmetric multiprocessor systems and distributed systems are discussed and the parallel performance of the proposed schemes is given, using MPI, OpenMP and Java multithreading.