Symmetrical Multilevel Inverter Topology Research Articles

Performance analysis for induction motor fed by reduced switch symmetrical multilevel inverter topology

Due to its capacity to supply more voltage levels than conventional 2-level inverters, multilevel inverters have attracted a lot of attention in recent years. Multilevel inverters may produce output waveforms that nearly approximate sinusoidal waveforms because to this characteristic, which also significantly lowers harmonic distortion. In many different power conversion systems, the introduction of reduced switch symmetrical multilevel inverter topologies has drawn significant interest. Numerous benefits, such as higher output voltage quality, reduced harmonic distortions, and increased power conversion efficiency, are provided by these novel topologies. The inclusion of these inverters in the feeding of induction motors is one of their many prominent uses. In this paper, a generalized topology is presented that generates nine levels using nine switching devices. To reduce complexity, switching pulses are generated using a low frequency pulse width modulation technique. MATLAB/Simulink is used to analyze the performance assessment of a unique three-phase symmetric cascaded multilevel inverter-based reduced switch symmetrical inverter fed induction motor drive, brushless DC (BLDC) motor and grid has been verified. According to the findings the total harmonic distortion (THD) is found to be 15% for a three-phase system and as the number of levels increases to 17 level the THD is 7.10%.

Solar PV based seventeen level reduced switch symmetrical multilevel inverter topology fed induction motor

Multilevel inverters have received a lot of interest in recent years due to their ability to deliver more voltage levels than typical two-level inverters. Because of this property, multilevel inverters can produce output waveforms that closely resemble sinusoidal waveforms, lowering harmonic distortion dramatically. The emergence of reduced switch symmetrical multilevel inverter topologies has developed the curiosity of many different power conversion systems. These new topologies offer numerous advantages, including greater output voltage quality, fewer harmonic distortions, and increased power conversion efficiency. The inclusion of these inverters in the feeding of induction motors is one of their many prominent uses. A 17 levels of multi-level inverter (MLI) topology is presented with reduced switch count and harmonic reduction for power quality improvement. The inverter is fed by isolated equal photovoltaic panels which act as direct current or DC source. To reduce complexity, switching pulses are generated using hybrid pulse width modulation technique which is designed as controller. Through the use of MATLAB/Simulink, the performance assessment of a unique cascaded multilevel inverter-based reduced switch symmetrical inverter feeding an induction motor drive has been verified. The harmonic distortion with reduced switches obtained is 7.47% which is comparatively less than when compared with conventional cascaded H-bridge topology.

Design and Development of N-Level Symmetrical Multilevel Inverter Topology with Reduced Switches

In this paper, 11-level multilevel inverter with reduced power switch configuration is developed and investigated. This proposed configuration can be extended for [Formula: see text] levels with the required number of power switches. Comparative analysis between the proposed multilevel inverter topology and well-known existing multilevel inverter topologies is carried out. Fundamental switching angle calculation for the power switches of the proposed topology has been optimized using black widow optimization algorithm technique and also the proposed topology has been tested with the classical multicarrier alternative phase opposition disposition PWM technique. To test the effectiveness of the proposed topology, different tests have been conducted such as testing with different modulation indexes, DC input voltages, load settings and voltage ride-through capabilities. This paper presents various simulation and experimental results under various operating conditions to prove the performance of the proposed multilevel inverter topology.

Mathematical analysis of cost function and reliability condition for new proposed multilevel inverter topology

<span>In this paper cost function and reliability analysis of classic novel symmetric multilevel inverter topology has been presented. Cost function and reliability analysis are the economical factors of the effieciency of an inverter, this made the intrest in this area.cost function deneotes the cost of the inverter based on the power flow, reliability explain the mean time failure propotional to the life span. Firstly the cost function of the novel topology has been proposed using mathematical calculation using various current rating and the results are validated compared with exiting topology. Secondly reliability approach is used to evaluate the reliability of the switch with respect to the failure rate and mean time period of the switch using fedis and markow reliability analysis equations and the results are evaluated for all the switches present in the topology. And the results are the compared with the conventional multilevel inverter, cost function and reliability analysis of the proposed multilevel inverter.</span>

A Symmetrical Multilevel Inverter Topology with Minimal Switch Count and Total Harmonic Distortion

A multilevel inverter (MLI) with reduced number of power devices, especially for the higher output levels, is presented in this paper. The generalized topology for ([Formula: see text]) level MLI is developed with symmetrical isolated dc sources and ([Formula: see text]) number of switches. A five-level MLI is developed with five power switches and then by adding each one additional switch two more levels are added in the output voltage waveform. With the help of lookup table, the working principle of the proposed five-level MLI topology is explained. Sinusoidal pulse width modulation–phase disposition control technique has been used to get a minimal total harmonic distortion (THD). The proposed MLI topology is simulated on the MATLAB platform. The laboratory prototype is developed for five-level MLI, and the experimental results obtained validate the simulation studies. The dSPACE 1104 is used for generating gate pulses in case of experimentation. The output voltage and current THDs obtained are 9.20% and 4.60%, respectively; the harmonics are mitigated more with five-level inverter. The proposed topology is compared with the cascaded H-bridge multilevel inverter.

A New Symmetric Multilevel Inverter Topology Using Single and Double Source Sub-Multilevel Inverters

In recent years, the multilevel converters have been given more attention due to their modularity, reliability, failure management and multi stepped output waveform with less total harmonic distortion. This paper presents a novel symmetric multilevel inverter topology with reduced switching components to generate a high quality stepped sinusoidal voltage waveform. The series and parallel combinations of switches in the proposed topology reduce the total number of conducting switches in each level of output voltages. In addition, a comparison between the proposed topology with another topology from the literature is presented. To verify the proposed topology, the computer based simulation model is developed using MATLAB/Simulink and experimentally with a prototype model results are then compared.