Symbol-level Precoding Techniques Research Articles

Design Optimization for Low-Complexity FPGA Implementation of Symbol-Level Multiuser Precoding

This paper proposes and validates a low-complexity FPGA design for symbol-level precoding (SLP) in multiuser multiple-input single-output (MISO) downlink communication systems. In the optimal case, the symbol-level precoded transmit signal is obtained as the solution to an optimization problem tailored for a given set of users’ data symbols. This symbol-by-symbol design, however, imposes excessive computational complexity on the system. To alleviate this issue, we aim to reduce the per-symbol complexity of the SLP scheme by developing an approximate yet computationally-efficient closed-form solution. The proposed solution allows us to achieve a high symbol throughput in real-time implementations. To develop the FPGA design, we express the proposed solution in an algorithmic way and translate it to hardware description language (HDL). We then optimize the processing to accelerate the performance and generate the corresponding intellectual property (IP) core. We provide the synthesis report for the generated IP core, including performance and resource utilization estimates and interface descriptions. To validate our design, we simulate an uncoded transmission over a downlink multiuser channel using the LabVIEW software, where the SLP IP core is implemented as a clock-driven logic (CDL) unit. Our simulation results show that a throughput of 100 Mega symbols per second per user can be achieved via the proposed SLP design. We further use the MATLAB software to produce numerical results for the conventional zero-forcing (ZF) and the optimal SLP techniques as benchmarks for comparison. Thereby, it is shown that the proposed FPGA implementation of SLP offers an improvement of up to 50 percent in power efficiency compared to the ZF precoding. Remarkably, it enjoys the same per-symbol complexity order as that of the ZF technique. We also evaluate the loss of the real-time SLP design, introduced by the algebraic approximations and arithmetic inaccuracies, with respect to the optimal scheme.

FPGA Acceleration for Computationally Efficient Symbol-Level Precoding in Multi-User Multi-Antenna Communication Systems

In this paper, we demonstrate an FPGA-accelerated design of the computationally efficient symbol-level precoding (SLP) for high-throughput communication systems. The SLP technique recalculates the optimal beam-forming vectors by solving a non-negative least squares problem per every set of transmitted symbols. It exploits the advantages of constructive inter-user interference to minimize the total transmitted power and increase service availability. The benefits of using SLP come with a substantially increased computational load at the gateway. The FPGA design enables the SLP technique to perform in real-time operation mode and provide a high symbol throughput for the multiple receive terminals. We define the SLP technique in a closed-form algorithmic expression and translate it to hardware description language (HDL) and build an optimized HDL core for an FPGA. We evaluate the FPGA resource occupation, which is required for the high throughput multiple-input-multiple-output (MIMO) systems with sizeable dimensions. We describe the algorithmic code, the I/O ports mapping, and the functional behavior of the HDL core. We deploy the IP core to an actual FPGA unit and benchmark the energy efficiency performance of the SLP. The synthetic tests demonstrate a fair energy efficiency improvement of the proposed closed-form algorithm compared to the best results obtained through the MATLAB numerical simulations.

Symbol-Level Precoding for Low Complexity Transmitter Architectures in Large-Scale Antenna Array Systems

In this paper, we consider three transmitter designs for symbol-level-precoding (SLP), a technique that mitigates multiuser interference (MUI) in multiuser systems by designing the transmitted signals using the channel state information and the information-bearing symbols. The considered systems tackle the high hardware complexity and power consumption of existing SLP techniques by reducing or completely eliminating fully digital radio frequency (RF) chains. The first proposed architecture referred to as, Antenna Selection SLP, minimizes the MUI by activating a subset of the available antennas and thus, reducing the number of required RF chains to the number of active antennas. In the other two architectures, which we refer to as RF domain SLP, the processing happens entirely in the RF domain, thus eliminating the need for multiple fully digital RF chains altogether. Instead, the analog phase shifters directly modulate the signals on the transmit antennas. The precoding design for all the considered cases is formulated as a constrained least squares problem and efficient algorithmic solutions are developed via the Coordinate Descent method. Simulations provide insights into the power efficiency of the proposed schemes and the improvements over the fully digital counterparts.