Switched-opamp Technique Research Articles

A 0.6-V pseudo-differential OTA with switched-opamp technique for low power applications

A low-voltage, pseudo-differential OTA is presented in this study for power-effective applications. The cross-coupled common-mode feedforward (CMFF) technique is proposed to improve the CMRR performance and double transconductance of pseudo-differential OTA with the same power consumption as the conventional one. Implemented under the supply voltage of 0.6 V, the designed OTA, which converts the single-ended signal into the fully differential signal, is used as the input buffer of ADC. Considering the particularity of ADC application, switched-opamp (SO) technology is designed to turn off amplifier partly for compromising high power efficiency and short start time. Implemented in the 0.18-μm standard CMOS process, the OTA occupies an active chip area of 0.05 mm2 and provides the settling time of 310 ns with 0.1% accuracy for 0.6 Vpp output step. The measured input noise spectrum density is −147 dBv/Hz (45 nv/Hz) @ 25 MHz. The output-referred integrated noise voltage is 485 μV from 20 Hz to 25 MHz.

A 1.1V 12μW 86dB DR Sigma-Delta Modulator for Health Monitoring System

A low-voltage low-power Sigma-Delta modulator for health monitoring system is designed using a standard 0.18[Formula: see text][Formula: see text]m CMOS technology. To achieve high accuracy with low power consumption in low supply voltage environment, the designed modulator is implemented with a one-bit third-order topology, in which the input-feedforward structure and switched-opamp (SO) technique are combined. Using the proposed design method, the SO meets the system requirements with the minimal power consumption and good stability in a feedback loop. The modulator achieves 86[Formula: see text]dB dynamic range (DR) over a 300[Formula: see text]Hz bandwidth with an oversampling ratio (OSR) of 128, while it occupies 0.16[Formula: see text]mm2 and consumes 12[Formula: see text][Formula: see text]W under a 1.1[Formula: see text]V supply.

모바일 기기용 BMIC를 위한 2차 시그마 델타 모듈레이터

본 논문에서는 모바일 기기의 배터리 전력관리 IC(Battery Management IC)에서 전압 및 온도를 측정하여 디지털 신호로 바꾸어 주는데 필요한 시그마-델타 모듈레이터를 설계하였다. 제안하는 이산-시간 시그마-델타 모듈레이터는 2차의 단일 비트 구조이고 0.13um CMOS 공정으로 제작되었다. 모듈레이터의 소모전류를 줄이기 위하여 switched-opamp 방식을 적용하여 설계하였다. 제안하는 모듈레이터는 오버 샘플링 비율이 256 일 때 256kHz의 클락 주파수에서 83-dB의 dynamic range와 81.7dB의 peak signal-to-(noise + distortion) ratio(SNDR)를 가진다. 3.3 V의 전원전압에서 0.66 mW의 전력을 소모하며 모듈레이터 코어의 면적은 <TEX>$0.425mm^2$</TEX> 이다. This paper presents design of the second-order sigma-delta modulator for converting voltage and temperature signals to digital ones in Battery Management IC (BMIC) for mobile applications. The second-order single-loop switched-capacitor sigma-delta modulator with 1-bit quantization in 0.13-um CMOS technology is proposed. The proposed modulator is designed using switched-opamp technique for saving power consumption. With an oversampling ratio of 256 and clock frequency of 256kHz, the modulator achieves a measured 83-dB dynamic range and a peak signal-to-(noise+distortion) ratio (SNDR) of 81.7dB. Power dissipation is about 0.66 mW at 3.3 V power supply and the occupied core area is <TEX>$0.425mm^2$</TEX>.

A 900 mV Single-Stage Class-AB Amplifier for a .SIGMA.-.DELTA. Modulator with the Switched-Opamp Technique

A 900 mV single-stage class-AB amplifier suitable for the Switched-Opamp technique is presented. To improve the slew-limited characteristics, a Dynamic Current Source (DCS) circuit which boosts the tail currents of the amplifier is proposed. The tail current of the proposed circuit is well defined and independent of technology parameters and supply variations. The tail current of the amplifier is 40 μA with zero differential voltages, while the maximum output current is nearly 900 μA. A single-loop 3rd order Σ-Δ modulator with the proposed amplifier was designed. For a 260 mV 15.625 kHz sinusoidal input signal, the simulated dynamic range of the modulator is 89 dB.

A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture

SUMMARY This paper proposes a low-voltage high-speed sampleand-hold (S/H) structure with excellent power efficiency. Based on the switched-opamp technique, an inverse-flip-around architecture which maximizes the feedback factor is employed in the proposed S/H. A skew-insensitive double-sampling mechanism is presented to increase the throughput by a factor of two while eliminating the timing mismatch associated with double-sampling circuits. Furthermore, a dual-input dual-output opamp is proposed to incorporate double-sampling into the switched-opamp based S/H. This opamp also removes the memory effect in double-sampling circuitry and features fast turn-on time to improve the speed performance in switched-opamp circuits. Simulation results using a 0.13-μm CMOS process model demonstrates the proposed S/H circuit has a total-harmonic-distortion of −67.3 dB up to 250 MSample/ sa nd a0 .8VPP input range at 0.8 V supply. The power consumption is 3.5 mW and the figure-of-merit is only 7.4 fJ/step.

Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture

This paper proposes useful circuit structures for achieving a low-voltage/low-power pipelined ADC based on switched-opamp architecture. First, a novel unity-feedback-factor sample-and-hold which manipulates the features of switched-opamp technique is presented. Second, opamp-sharing is merged into switched-opamp structure with a proposed dual-output opamp configuration. A 0.8-V, 9-bit, 10-Msample/s pipelined ADC is designed to verify the proposed circuit. Simulation results using a 0.18-μm CMOS 1P6M process demonstrate the figure-of-merit of this pipelined ADC is only 0.71pJ/step.

A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture

A 1-V, 8-bit pipelined ADC is realized using multi-phase switched-opamp (SO) technique. A novel loading-free architecture is proposed to reduce the capacitive loading and to improve the speed in low-voltage SO circuits. Employing the proposed loading-free pipelined ADC architecture together with double-sampling technique and a fast-wake-up dual-input-dual-output switchable opamp, the ADC achieves 100-MS/s conversion rate, which to our knowledge is the fastest ADC ever reported at 1-V supply using SO technique, with performance comparable to that of many high-voltage switched-capacitor (SC) ADCs. Implemented in a 0.18-mum CMOS process, the ADC obtains a peak SNR of 45.2 dB, SNDR of 41.5 dB, and SFDR of 52.6 dB. Measured DNL and INL are 0.5 LSB and 1.1 LSB, respectively. The chip dissipates only 30 mW from a 1-V supply

A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters

This paper presents a partially switched-opamp technique for a high-speed, low-power pipelined analog-to-digital converter (ADC). Unlike a conventional switched-opamp technique, only the second stage of a two-stage opamp is switched with the enhanced power efficiency and the drawbacks of an opamp sharing technique and a conventional switched-opamp technique are addressed. The prototype of 8-bit 200-MS/s pipelined ADC is implemented in a 0.18-/spl mu/m CMOS process technology. This converter achieves 55.8-dB spurious free dynamic range, 47.3-dB signal-to-noise-plus-distortion ratio, 7.68 effective number of bits for a 90-MHz input at full sampling rate, and consumes 30-mW from a 1.8-V supply. The active area of the ADC is 0.15 mm/sup 2/.

A 1-v 3.5-mW CMOS switched-opamp quadrature if circuitry for bluetooth receivers

A 1-V switched-capacitor (SC) quadrature IF circuitry for Bluetooth receivers is demonstrated using switched-opamp technique. To achieve double power efficiency while maintaining low sensitivity to finite opamp gain effects for the SC IF circuitry, half-delay integrator-based filters and /spl Sigma//spl Delta/ modulator have been proposed. The proposed quadrature IF circuitry employs a seventh-order IF filter for channel selection and a third-order /spl Sigma//spl Delta/ modulator for analog-to-digital conversion. A noise-shaping extension technique is employed to enhance the resolution of the low-pass /spl Sigma//spl Delta/ modulator by 16 dB while operating at the same oversampling ratio and power consumption. At a 1-V supply, the quadrature IF circuitry achieves a measured IIP3 of -3 dBm at a nominal gain of 24 dB with a 48-dB variable gain control while consuming a total power dissipation of 3.5 mW.

A Sub-1V Fourth-Order Bandpass Delta-Sigma Modulator

A sub-1V fourth-order bandpass delta-sigma modulator is presented in this paper. Using the switched opamp technique enables the modulator to operate at only 0.8 V supply voltage without using volta...

A 0.7-V MOSFET-only switched-opamp ΣΔ modulator in standard digital CMOS technology

A 0.7-V MOSFET-only /spl Sigma//spl Delta/ modulator for voice band applications is presented. The second-order modulator is realized using a switched-opamp technique. All capacitors are realized using compensated MOS devices operated in the depletion region. A combination of parallel and series compensated depletion-mode MOSCAPs is used to obtain high area efficiency. The circuit is fabricated in a 0.18-/spl mu/m CMOS process. The only components used are standard n-MOS and p-MOS transistors with threshold voltages of approximately 400 mV. All transistors are operated within the supply voltage window of 0.7 V; voltage boosting techniques are not used. The active area is 0.082 mm/sup 2/. The modulator achieves 67-dB signal-to-noise-and-distortion ratio, 70-dB signal-to-noise ratio, and 75-dB dynamic range at 8-kHz signal bandwidth and consumes 80 /spl mu/W of power.

A 1-V 10.7-MHz switched-opamp bandpass ΣΔ modulator using double-sampling finite-gain-compensation technique

A 1 V switched-capacitor (SC) bandpass sigma-delta (/spl Sigma//spl Delta/) modulator is realized using a high-speed switched-opamp (SO) technique with a sampling frequency of up to 50 MHz, which is improved ten times more than prior 1 V SO designs and comparable to the performance of the state-of-the-art SC circuits that operate at much higher supply voltages. On the system level, a fast-settling double-sampling SC biquadratic filter architecture is proposed to achieve high-speed operation. A low-voltage double-sampling finite-gain-compensation technique is employed to realize a high-resolution /spl Sigma//spl Delta/ modulator using only low-DC-gain opamps to maximize the speed and to reduce power dissipation. On the circuit level, a fast-switching methodology is proposed for the design of the switchable opamps to achieve a switching frequency up to 50 MHz. Implemented in a 0.35-/spl mu/m CMOS process (V/sub TP/=0.82 V and V/sub TN/=0.65 V) and at 1 V supply, the modulator achieves a measured peak signal-to-noise-and-distortion ratio (SNDR) of 42.3 dB at 10.7 MHz with a signal bandwidth of 200 kHz, while dissipating 12 mW and occupying a chip area of 1.3 mm/sup 2/.

Design of low-voltage front-end interface for switched-op amp circuits

Switched-op amp technique is an effective technique for designing low-voltage switched-capacitor circuits. The only drawback with this approach is the difficulty in designing the front-end interface to the external input, In this paper, front-end interface structures with wide signal swing and no voltage boosting are proposed. Based on a conventional 1.2-/spl mu/m CMOS process, a front-end interface was designed and implemented. For a 1-V supply, the interface dissipates 80 /spl mu/W. The track mode THD was measured to be -78 dB for a 600-mV peak-to-peak output suing, and the maximum sampling rate was measured to be 600 kS/s for a capacitive load of 20 pF.

1-V 9-bit pipelined switched-opamp ADC

A 9-bit 1.0-V pipelined analog-to-digital converter has been designed using the switched-opamp technique. The developed low-voltage circuit blocks are a multiplying analog-to-digital converter (MADC), an improved common-mode feedback circuit for a switched opamp, and a fully differential comparator. The input signal for the converter is brought in using a novel passive interface circuit. The prototype chip, implemented in a 0.5-/spl mu/m CMOS technology, has differential nonlinearity and integral nonlinearity of 0.6 and 0.9 LSB, respectively, and achieves 50.0-dB SNDR at 5-MHz clock rate. As the supply voltage is raised to 1.5 V, the clock frequency can be increased to 14 MHz. The power consumption from a 1.0-V supply is 1.6 mW.

Design and power optimization of high-speed pipeline ADC for wideband CDMA applications

This paper presents a 7-bit 64 MS/s pipeline A/D converter suitable for wideband CDMA applications. Targeting at achieving low power dissipation at high speed, techniques such as digital correction and optimal scaling of capacitor value have been employed. Switched-Opamp technique is used to further reduce power consumption. This ADC is implemented in 0.5 μm standard CMOS process. It operates from a single 3 V supply, and dissipates only 31 mW at 64 MS/s.

Low-voltage fully differential switched-opamp bandpass modulator

The paper deals with the design of a low-voltage bandpass ΣΔ modulator implemented with the switched-capacitor technique. To use standard technology (no low-threshold devices) and without an on-chip voltage multiplier, the switched-opamp technique has been adopted. The basic building blocks for the construction of a ΣΔ modulator (SC integrator, quantiser, and feedback DAC) are proposed in a fully differential version. In addition, they have been improved with respect to those previously reported to give a larger output swing at a higher sampling frequency and without any voltage reference. The validity of the proposed circuits is demonstrated by the realisation of a second-order bandpass ΣΔ modulator operating with a single 1 V supply within a standard 0.5 µm CMOS technology (VTHn = 0.65 V, VTHp = 0.7 V). The modulator operates at a sampling frequency of 1.8 MHz with a full-scale input range of 2 Vpk-pk and achieves a 45 dB dynamic range in a 20 kHz bandwidth.

A 1.5-V-100-μW ΔΣ modulator with 12-b dynamic range using the switched-opamp technique

The design and implementation of a very low supply voltage/low power /spl Delta//spl Sigma/ modulator is presented. It is based on the switched-opamp technique, which allows low voltage operation with a standard process and without voltage multiplication. The design methodology is illustrated with a second-order single-loop /spl Delta//spl Sigma/ modulator. The chip is implemented in a 0.7-/spl mu/m CMOS process with standard threshold voltages. The power supply is 1.5 V and the power dissipation is only 100 /spl mu/W. The measured dynamic range in the speech bandwidth of 300-3400 Hz is 12 b. The total harmonic distortion (THD) is lower than -72 dB.

900 mV differential class AB OTA for switched opamp applications

A novel fully differential class AB OTA in standard CMOS for application with the switched opamp technique is presented. It makes use of a current buffer loop in the input stage as a low voltage current mirror. A new common mode feedback error amplifier, especially suited for the class AB OTA, is also presented. It is based on a differential stage of which the concept is introduced here. A totally new way of switching the amplifiers is introduced as well. Simulations demonstrate the operation of these novel circuits down to a 900 mV supply voltage.

A 1-V 1.8-MHz CMOS switched-opamp SC filter with rail-to-rail output swing

A low-voltage switched capacitor (SC) filter operated from a single 1 V supply and realized in a standard 0.5-/spl mu/m CMOS technology is presented. Proper operation is obtained using the switched-opamp technique without any clock voltage multiplier or low-threshold devices. This makes the circuit compatible with future deep submicrometer technology. As opposed to previous switched-opamp implementations, the filter uses a fully differential topology. This allows operation with a rail-rail output swing and reduction of the number of opamps required to build high order infinite impulse response (IIR) filters. On the other hand, a low-voltage common-mode feedback (CMFB) circuit is required. In addition, the circuit uses an opamp which is only partially turned off during the off phase. This enables an increase in the maximum sampling frequency. The filter implements a bandpass response (f/sub s//f/sub o/=4, Q=7) and it has been characterized with a 1.8 MHz sampling frequency. Its power consumption is about 160 /spl mu/W. The filter is still fully functional down to 0.9 V supply voltage.

Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages

The implementation of analog CMOS circuits that operate in the very low power supply voltage range (1 V to 2 V) becomes more important nowadays. Most accurate filter circuits are designed in the switched-capacitor technique. The existing design techniques require, however, the on-chip generation of a higher voltage by means of a voltage multiplier. In this paper, a novel technique, derived from the standard switched-capacitor technique, is presented. It is called switched-opamp because it is based on the replacement of the critical switches with opamps which are turned on and off. This technique results in a true, very low voltage operation without the need for voltage multipliers. As an example, a second order lowpass switched-capacitor filter is implemented in the switched-opamp technique. This filter operates with only a 1.5 V power supply. It is realized in a 2.4-/spl mu/m CMOS process with V/sub T/=/spl plusmn/0.9 V. It has a measured total harmonic distortion of -60 dB for a signal swing of 600 mV/sub ptp/ and a powerdrain of only 110 /spl mu/W.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>