Switched-capacitor Voltage Converter Research Articles

A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI

This work demonstrates a dual-core RISC-V system-on-chip (SoC) with integrated fine-grain power management. The 28-nm fully depleted silicon-on-insulator (FD-SOI) SoC integrates switched-capacitor voltage converters and 4-Gb/s off-chip serial links. The SoC runs applications with operating system support on dual RISC-V Rocket cores with vector accelerators. Runtime monitoring of microarchitectural counters allows prediction of future compute intensity, enabling the voltage state of the managed core to be adjusted quickly to optimize energy efficiency without sacrificing overall performance.

A Switched Capacitor Voltage Converter With Exponentially Sized Capacitor Banks for Wide Load Range

Modern Internet-of-Things (IoT) applications need voltage converters to efficiently supply power with a small active period at various load conditions. The energy losses in such voltage converters during transitions between sleep-active can be significant, especially when the converters deviate from their optimum load conditions. The proposed Switched Capacitor (SC) converter, fully integrated on chip, incorporates Split-Capacitor Charging (SCC) and Energy Recycling (ER) techniques to minimize the energy losses during the transitions. The converter consists of multiple capacitor banks and their size increases in a binary exponential fashion. It employs an LDO to support a wide range of output voltage levels and reduce output voltage ripple during energy recycling and Continuous phase. In addition, we introduce an efficient test circuit structure using an on-chip digital controller and reconfigurable load circuit. This test structure can eliminate the unwanted parasitic values and varying delays, which are commonly incurred in the conventional test structures of on-chip voltage converters with off-chip loads and external control signal generation. We implemented the proposed voltage converter with a complete on-chip test structure using a 0.13 $\mu {\mathrm{ m}}$ CMOS process. Measurement results demonstrate a maximum efficiency of 86.83 % for a load current of $11~\mu \text{A}$ . It also achieved an improvement of 64.44 % in energy efficiency over conventional voltage converters for a short active period.

At random

at random

An Energy Efficient Charging Technique for Switched Capacitor Voltage Converters With Low-Duty Ratio

Charging a capacitor array of a switched-capacitor (SC) dc-dc converter, supplying load circuits with a very short active period, can be pivotal to achieve high energy efficiency of its operation. This is because the capacitors may lose most of the stored energy during a long sleep period, and thus every sleep-to-active transition requires full recharging of the capacitors. In this brief, we present an energy efficient capacitor charging technique called split-capacitor charging, which charges a capacitor array in a step-wise fashion. Circuit simulations demonstrate that the proposed technique can reduce the energy wastage during sleep-to-active transition up to 66%. When tested on load circuits with a short active period, a voltage converter employing the proposed charging method shows up to 24% improvement in energy efficiency over conventional SC converters.

Exploiting Voltage Regulators to Enhance Various Power Attack Countermeasures

The security implications of on-chip voltage regulation on the effectiveness of various voltage/frequency scaling-based countermeasures such as random dynamic voltage and frequency scaling (RDVFS), random dynamic voltage scaling (RDVS), and aggressive voltage and frequency scaling (AVFS) are investigated. The side-channel leakage mechanisms of different on-chip voltage regulator topologies are mathematically analyzed and verified with circuit level simulations. Correlation coefficient between the input data and monitored power consumption of a cryptographic circuit is used as the security metric to compare the impact of different on-chip voltage regulators when implemented with the aforementioned countermeasures. As compared to a cryptographic circuit without countermeasure, the RDVFS technique implemented with an on-chip switched-capacitor voltage converter reduces the correlation coefficient over 80 percent and over 92 percent against differential and leakage power analysis attacks, respectively, through masking the leakage of the clock frequency and supply voltage information in the monitored power profile.

Charge-Withheld Converter-Reshuffling: A Countermeasure Against Power Analysis Attacks

Converter-reshuffling (CoRe) technique has recently been proposed as a power-efficient countermeasure against differential power analysis (DPA) attacks by randomly reshuffling the individual stages within a multiphase switched-capacitor voltage converter. This randomized reshuffling of the converter stages inserts noise to the monitored power profile and prevents an attacker from extracting the correct input power data. The total number of activated phases within a switch period, however, still correlates with the dynamic power consumption of the workload. To break the one-to-one relationship between the monitored and actual power consumption, a charge-withheld CoRe technique is proposed in this brief by utilizing the flying capacitors to withhold a random amount of charge for a random time period. As compared to the conventional CoRe technique, the proposed charge-withheld CoRe technique eliminates the possibility of having a zero power trace entropy (PTE) even under machine-learning-based DPA attacks. The average PTE of the monitored power profile is increased ∼46.1% with a 64-phase charge-withheld CoRe technique.

Time-Delayed Converter-Reshuffling: An Efficient and Secure Power Delivery Architecture

In this letter, a time-delayed converter-reshuffling (CoRe) technique is proposed as a countermeasure against machine learning based differential power analysis (DPA) attacks where the attacker can synchronize the sampling frequency with the operating frequency of the device under attack. The proposed time-delayed CoRe technique exploits the distributed nature of multiphase switched capacitor voltage converters where half of the converter stages are delayed to eliminate the risk of having zero power trace entropy (PTE) under machine learning based DPA attacks. A high PTE value is maintained (above 3.2 for a 64-phase time-delayed CoRe technique) regardless of the phase difference between the attacker’s sampling rate and the operating frequency. In addition, the minimum PTE value of the proposed time-delayed CoRe technique is enhanced from zero to $ \sim 3$ by inserting a certain time-delay to half of the converter stages.

Converter-Gating: A Power Efficient and Secure On-Chip Power Delivery System

Dynamic power management techniques and related voltage converter architectures are proposed to design a secure and efficient on-chip power delivery system. A new power management technique, converter-gating, that adaptively turns on and off individual stages of an interleaved switched-capacitor voltage converter based on the workload information to improve the voltage conversion efficiency is proposed. Converter-gating technique is further utilized as a countermeasure against side channel power analysis attacks by pseudo-randomly controlling the converter activity. A new method is proposed to improve the response time of the converter during transient load changes by adaptively configuring the conversion ratio of a switched capacitor voltage converter. The proposed converter is designed and verified using IBM 130 nm technology kit. The proposed system achieves 5% higher power conversion efficiency compared to conventional converters, improves the response time to transient load changes from 1.4 $\mu{\rm s}$ to 104 ns and reduces the correlation between the input current and load current.

Voltage Regulator Dc_Dc Converter Based On Filter for Low Power Analysis

An active filter-based on-chip DC-DC voltage converter for application to distributed on-chip power supplies in multivoltage systems is described in this paper. No inductor or output capacitor is required in the proposed converter. The area of the voltage converter is therefore significantly less than that of a conventional low-dropout (LDO) regulator. Hence, the proposed circuit is appropriate for point-of-load voltage regulation for noise sensitive portions of an integrated circuit. The performance of the circuit has been verified with Cadence Spectre simulations and fabricated with a commercial 110 nm complimentary metal oxide semiconductor (CMOS) technology. The area of the voltage regulator is 0.015 mm2 and delivers up to 80 mA of output current. The transient response with no output capacitor ranges from 72 to 192 ns. The parameter sensitivity of the active filter is also described. The advantages and disadvantages of the active filter-based, conventional switching, linear, and switched capacitor voltage converters are compared. The proposed circuit is an alternative to classical LDO voltage regulators, providing a means for distributing multiple local power supplies across an integrated circuit while maintaining high current efficiency and fast response time within a small area. Key points: Hybrid regulator, low dropout regulator, on-chip voltage regulation, point-of-load voltage egulation. I. Introduction The power supply voltage aggressively scales with each technology generation, making the delivery of a high quality supply voltage to noise sensitive circuit blocks highly challenging .The number of voltage domains within an integrated circuit is increasing to satisfy stringent power budgets. The increase in the number of voltage domains requires new techniques to generate these voltages close to the load circuitry while occupying a small area. The power savings is greater when the voltage regulators are close to the load devices (point-of-load voltage delivery), and size is therefore the primary issue for point-of-load voltage regulation. Classical power supplies occupy large on-chip area and are therefore not appropriate for point-of-load power delivery. Several topologies are commonly used to generate on-chip dc voltages. These DC-DC voltage converters are generally used as on-chip power supplies in high performance integrated circuits. Conventional DC-DC converters can be grouped into three primary categories: switching, switched capacitor (SC), and linear DC-DC converters . Buck converters, which are step-down switching DC-DC converters, are popular because of their high power efficiency. A second order inductor-capacitor (LC) passive filter is commonly used in a buck converter. The passive LC components require significant on-chip area, therefore, the passive components have generally been implemented offchip. As a consequence of placing these components off-chip, significant voltage drop and bounce are produced at the package level due to the parasitic resistance and inductance between the off-chip components of the voltage converter and the integrated circuit. Additionally, the parasitic interconnect impedance between the discrete components of the voltage converter can produce significant power loss. Furthermore, with power supply scaling, analog and digital circuits are less tolerant to fluctuations in the supply voltage . The parasitic impedance of the interconnect between the discrete components degrades the speed and accuracy of the load regulation, causing slow response times and changing output voltage levels. A more area efficient voltage converter structure is a lowdropout voltage regulator (LDO) . These regulators are implemented on-chip close to the load circuitry for fast and accurate load regulation. These regulators require a large output capacitance to achieve fast load regulation. This capacitor occupies significant on-chip area and is therefore generally implemented off-chip . The off-chip implementation of the output capacitor requires dedicated I/Os and produces higher parasitic losses. Alternatively, when the output capacitor is placed on-chip, the output capacitor dominates the total LDO regulator area . A high bias current of 6 mA is used in to deliver 100 mA current with a 600 pF output capacitor. This approach is not appropriate for low power applications and the output capacitor occupies a significant die area. Many techniques have been proposed to eliminate the need for the large off-chip capacitor without sacrificing the stability and performance

Active Filter-Based Hybrid On-Chip DC–DC Converter for Point-of-Load Voltage Regulation

An active filter-based on-chip DC-DC voltage converter for application to distributed on-chip power supplies in multivoltage systems is described in this paper. No inductor or output capacitor is required in the proposed converter. The area of the voltage converter is therefore significantly less than that of a conventional low-dropout (LDO) regulator. Hence, the proposed circuit is appropriate for point-of-load voltage regulation for noise sensitive portions of an integrated circuit. The performance of the circuit has been verified with Cadence Spectre simulations and fabricated with a commercial 110 nm complimentary metal oxide semiconductor (CMOS) technology. The area of the voltage regulator is 0.015 mm2 and delivers up to 80 mA of output current. The transient response with no output capacitor ranges from 72 to 192 ns. The parameter sensitivity of the active filter is also described. The advantages and disadvantages of the active filter-based, conventional switching, linear, and switched capacitor voltage converters are compared. The proposed circuit is an alternative to classical LDO voltage regulators, providing a means for distributing multiple local power supplies across an integrated circuit while maintaining high current efficiency and fast response time within a small area.

Power-supply circuits for ultralow-power subthreshold MOS-LSIs

A low-voltage power supply circuit is developed for micro-power CMOS LSI applications, especially for microwatt smart-sensor LSIs. The circuit consists of a switched-capacitor voltage converter and a series regulator. The switched converter lowers battery voltage 1.5-3V to a low voltage of 0.5-0.7V to drive the series regulator, and the series regulator provides LSI logic gates with a power voltage of 0.4-0.6V such that the logic gates operate in the subthreshold region. In a sample circuit designed to produce a supply voltage of 0.6V, the switched converter lowered a 1.5-V battery voltage to 0.68V, and the series regulator lowered the 0.68V to 0.6V. The power conversion efficiency of the switched converter was 83%, and the total efficiency was 73%, with a 13-µA output current.