Switched-capacitor Bandpass Filter Research Articles

A 270 nW Switched-Capacitor Acoustic Feature Extractor for Always-On Voice Activity Detection

This manuscript presents an ultra-low power acoustic feature extractor for always-on voice activity detection (VAD). It extracts voice features by a 10-band passive switched-capacitor (SC) bandpass filter (BPF) bank and digitizes the features using a passive SC envelope-to-digital converter at the low feature rate. The SC feature extractor minimizes the impact of process-voltage-temperature (PVT) variation at the circuit level, and is thereby free from costly chip-wise training or calibration while at the same time being capable of achieving a classification accuracy matching the state of the arts. Experimental results from a VAD feature extractor prototype fabricated in a 0.18-μm CMOS validate the effectiveness of the proposed techniques. It achieves an averaged 90%/86% speech/non-speech hit rates at 10 dB signal-to-noise ratio for all tested chips based on a universal classifier trained with data from one chip. The feature extractor is mostly passive and thus a low power consumption of 270 nW is achieved. In addition, the proposed feature extractor is frequency-scalable, which allows power-efficient multi-purpose acoustic system implementation.

A 0.9-V Analog-to-Digital Acquisition Channel for an IoT Water Management Sensor Node

This brief presents an analog front-end (AFE) specially developed for a water conductivity measurement system for water network management applications. Water conductivity is one of the best ways to detect a problem with the water in the network. In order to trigger an alarm it is only required to detect a 10% variation, which allows to simplify the system design. The proposed sensor uses four platinum micro-machined electrodes, where a 6 kHz signal is applied to the outer electrodes and a voltage signal is read in the inner ones. A programmable switched-capacitor (SC) bandpass filter is included in the analog-to-digital (A/D) channel to attenuate the interference from the 50 Hz power network, that shares the same environment with the water network, and to allow using a square wave signal to drive the sensor, thus simplifying the overall system. The resulting sine wave is digitized using a passive continuous-time (CT) 2nd order $\Delta\Sigma$ modulator. The output bitstream is decimated, using a sinc filter, and the RMS value of the voltage is calculated. The A/D acquisition channel was implemented in a 130 nm CMOS technology, using a supply voltage of 0.9 V and a clock frequency of 1 MHz (SC amplifier and SC bandpass filter) and 4 MHz ( $\Delta \Sigma $ modulator). Measurement results show a SNDR of 44.4 dB for an input signal of 6 kHz and an amplitude of −41 dBV. The channel dissipates 386 $\mu \text{W}$ and occupies an area of 0.27 mm2.

A 0.9-V Programmable Second-Order Bandpass Switched-Capacitor Filter for IoT Applications

This brief presents a programmable second-order bandpass switched-capacitor filter implemented for an Internet-of-Things water management sensor node. The filter circuit, which is based on the Sallen-Key topology, is implemented using a low-gain amplifier ( ${\boldsymbol \mu }\text{W}$ .

A Real-Time Harmonic Detection Method for Single-Phase Active Power Filters

Abstract: Harmonics, due to the increasing use of nonlinear loads, such as converters and solid state switching devices, has become a serious problem in power systems. Active power filters (APFs) have been used effectively to eliminate harmonic components. Precision of harmonic detection is one of the most important factors of APFs. This paper describes a novel circuit is proposed for real-time harmonic detection as an alternative to conventional approaches. This circuit is based on a switched capacitor band-pass filter and a Phase Locked Loop (PLL) which has low distortion sine wave output. This PLL follows not only phase of reference signal but also its amplitude. Harmonic components have been obtained by subtracting produced fundamental component with PLL from distorted signal. Fundamental and harmonic components of distorted line voltage and current have been successfully separated experimentally.

A 0.5-V low power analog front-end for heart-rate detector

This paper presents a low power analog front-end for heart-rate detector at a supply voltage of 0.5 V in 0.18 μm CMOS technology. A fully differential preamplifier is designed with a low power consumption of 300 nW. A 150 nW fourth order Switched-opamp switched capacitor bandpass filter is designed with passband 8---32 Hz. To digitize the analog signal, a low power second-order ΣΔ ADC is designed. The dynamic range and SNR of the converter are 46 dB and 54 dB respectively and it consumes a power of 125 nW. The overall front-end system including preamplifier, SO-SC bandpass filter, ΣΔ modulator and the biasing circuits are integrated and the total system consumes a power of 0.975 μW from 0.5 V supply.

64-Channel UWB Wireless Neural Vector Analyzer SOC With a Closed-Loop Phase Synchrony-Triggered Neurostimulator

An ultra wideband (UWB) 64-channel responsive neural stimulator system-on-chip (SoC) is presented. It demonstrates the first on-chip neural vector analyzer capable of wirelessly monitoring magnitude, phase and phase synchronization of neural signals. In a closed-loop, abnormal phase synchrony triggers the programmable-waveform biphasic current-mode neural stimulator. To implement these functionalities, the SoC integrates 64 neural recording amplifiers with tunable switched-capacitor (SC) bandpass filters, 64 multiplying 8-bit SAR ADCs, 64 programmable 16-tap FIR filters, a tri-core CORDIC processor, 64 biphasic current stimulation channels, and a 3.1-10.6 GHz UWB wireless transmitter onto a 4 mm × 3 mm 0.13 μm CMOS die. To minimize both the area and power dissipation of the SoC, the SAR ADC is re-used as a multiplier for FIR filtering and as a DAC and duty cycle controller for the biphasic neural stimulator. The SoC has been validated in the early detection and abortion of seizures in freely moving rodents on-line and in early seizure detection in humans off-line.

A new simple method for analysing of thermal noise in switched-capacitor filters

Thermal noise is one of the most important challenges in analogue integrated circuits design. This problem is more crucial in switched-capacitor (SC) filters due to the aliasing effect of wide-band thermal noise. In this article, a new simple method is proposed for estimating the power spectrum density of output thermal noise in SC filters, which have acceptable accuracy and short running time. In the proposed method, first using HSPICE simulator, accurate value of accumulated sampled noise on sampler capacitors in each clock state is achieved. Next, using difference equations of the SC filter, frequency response of the SC filter is shaped by time domain analysis. Based on the proposed method, a SC low-pass filter and a second-order SC band-pass filter are analysed. The results are validated by comparing to the previously measured data.

A parallel-architecture parametric equalizer for air-coupled capacitive ultrasonic transducers

Parametric equalization is rarely applied to ultrasonic transducer systems, for which it could be used on either the transmitter or the receiver to achieve a desired response. An optimized equalizer with both bump and cut capabilities would be advantageous for ultrasonic systems in applications in which variations in the transducer performance or the properties of the propagating medium produce a less-than-desirable signal. Compensation for non-ideal transducer response could be achieved using equalization on a device-by-device basis. Additionally, calibration of ultrasonic systems in the field could be obtained by offline optimization of equalization coefficients. In this work, a parametric equalizer for ultrasonic applications has been developed using multiple bi-quadratic filter elements arranged in a novel parallel arrangement to increase the flexibility of the equalization. The equalizer was implemented on a programmable system-on-chip (PSOC) using a small number of parallel 4th-order infinite impulse response switchedcapacitor band-pass filters. Because of the interdependency of the required coefficients for the switched capacitors, particle swarm optimization (PSO) was used to determine the optimum values. The response of a through-transmission system using air-coupled capacitive ultrasonic transducers was then equalized to idealized Hamming function or brick-wall frequencydomain responses. In each case, there was excellent agreement between the equalized signals and the theoretical model, and the fidelity of the time-domain response was maintained. The bandwidth and center frequency response of the system were significantly improved. It was also shown that the equalizer could be used on either the transmitter or the receiver, and the system could compensate for the effects of transmitterreceiver misalignment.

An approximation algorithm to improve capacitance matching in the design of SC filters

A critical issue in the design of switched-capacitor (SC) filters is the capacitance matching, because the filter coefficients depend on capacitance ratios. The most successful design method to achieve an accurate capacitance matching employs a parallel arrangement of identical unit capacitors to implement each filter capacitor. However, this procedure can be directly applied only if the filter coefficients can be written as rational numbers, since each capacitor is implemented as an integer number of unit capacitors in parallel. This paper presents a systematic procedure, with low computational effort, to approximate the filter coefficients by integer ratios causing acceptable errors in the filter frequency response, whereas keeping the total number of unit capacitors small, in order to save die area. This procedure was applied in the design of a sixth-order SC band-pass filter, which has been fabricated in a 0.35 μm CMOS technology. The fabricated filter occupies an area of 0.913 mm2, exhibits low sensitivity to fabrication process deviations and has an output dynamic range of 79.2 dB.

0.9 V low-power switched-opamp switched-capacitor bandpass filter for electroneurography acquisition systems

A 0.9 V fully differential switched-opamp-based sixth-order switched-capacitor bandpass filter, which has frequency response centred at 1.118 kHz with a Q of 0.235 and power saving by a proposed low-power biquad structure, is designed for electroneurography acquisition systems. It is implemented in a 0.18 µm CMOS technology with a normal threshold voltage of 0.48 V. The measured peak signal-to-noise ratio is 52 dB at 1 kHz sinusoid wave with input amplitude of 1 Vpp. In addition, the measured power-supply rejection ratio and common-mode rejection ratio are >40 dB in the desired bandwidth and have peak values of 70 and 67 dB, respectively. A dynamic range of 50 dB for total harmonic distortion of 3% is obtained while dissipating 262 µW and occupying a chip area of 0.35 mm2.

Nonlinear Shaping SC Oscillator With Enhanced Linearity

A nonlinear shaping technique for a switched-capacitor (SC) bandpass filter (BPF) based oscillator yielding enhanced linearity is presented. Usually, for an SC oscillator consisting of a BPF and a two-level comparator, the linearity can only be improved by increasing the quality factor (-factor) of the BPF. This paper proposes an efficient way to improve the linearity of SC BPF-based oscillators. In particular, by replacing the conventional two-level comparator by a sound multilevel comparator, a nonlinear shaping of the signal at the output of the comparator causes a significant improvement in linearity. To illustrate the effectiveness of the proposed technique, one conventional SC BPF-based oscillator and the proposed oscillator have been designed and fabricated in a standard 0.35- CMOS technology. Each oscillator was designed to operate from a 1.65 V supply voltage and a master clock frequency of 80 MHz. The oscillation frequency is 10 MHz and the -factor of the BPF is 10. Experimental results demonstrate that the proposed scheme improves the third-order harmonic distortion by 20 dB with respect to the conventional SC BPF-based oscillator.

Estimation of Aliasing Effects Due to Periodical Nonuniform Individual Sampling in High-<emphasis>Q</emphasis> Switched-Capacitor Filters

The periodical nonuniform individual sampling scheme has been shown suitable for capacitance spread and total capacitor area reduction in high quality (Q) factor switched-capacitor (SC) filters. However, the use of periodical nonuniform clock signals results in additional aliasing components in the output spectrum. This paper presents a simple model to analyze the generation of such alias components and gives practical expressions to estimate their power. The results are verified through circuit simulation of a 10.7-MHz second-order SC bandpass filter in a 0.35-mum CMOS technology. Implications on the use of this technique in the design of intermediate-frequency filters are discussed

A 10.7-MHz sixth-order SC ladder filter in 0.35-/spl mu/m CMOS technology

A sixth-order 10.7-MHz bandpass switched-capacitor filter based on a double terminated ladder filter is presented. The filter uses a multipath operational transconductance amplifier (OTA) that presents both better accuracy and higher slew rate than previously reported Class-A OTA topologies. Design techniques based on charge cancellation and slower clocks are used to reduce the overall capacitance from 782 down to 219 unity capacitors. The filter's center frequency and bandwidth are 10.7 MHz and 400 kHz, respectively, and a passband ripple of 1 dB in the entire passband. The quality factor of the resonators used as filter terminations is around 32. The measured (filter + buffer) third-intermodulation (IM3) distortion is less than -40 dB for a two-tone input signal of +3-dBm power level each. The signal-to-noise ratio is roughly 58 dB while the IM3 is -45 dB; the power consumption for the standalone filter is 42 mW. The chip was fabricated in a 0.35-mum CMOS process; filter's area is 0.84 mm2

Continuous-time common-mode feedback for high-speed switched-capacitor networks

This paper deals with the design of a continuous-time common-mode feedback (CMFB) for switched-capacitor networks. Its reduced input capacitance decreases the capacitive load at the output of the fully differential amplifier, improving its achievable gain-bandwidth (GBW) product and slew rate. This topology is more suitable for high-speed switched-capacitor applications when compared to a conventional switched-capacitor CMFB, enabling operation at higher clock frequencies. Additionally, it provides a superior rejection to the negative power supply noise (PSRR/sup -/). The performance of the CMFB is demonstrated in the implementation of a second-order 10.7-MHz bandpass switched-capacitor filter and compared with that of an identical filter using the conventional switched-capacitor CMFB (SC-CMFB). The filter using the continuous-time CMFB reduces the error due to finite GBW and slew rate to less than 1% for clock frequencies up to 72 MHz while providing a dynamic range of 59 dB and a PSRR/sup -/>22 dB. Both circuits were fabricated in 0.35-/spl mu/m CMOS technology.

An On-Chip Spectrum Analyzer for Analog Built-In Testing

This paper presents an analog built-in testing (BIT) architecture and its implementation. It enables the frequency response and harmonic distortion characterizations of an integrated device-under-test (DUT) through a digital off-chip interface. External analog instrumentation is avoided, reducing test time and cost. The proposed on-chip testing scheme uses a digital frequency synthesizer and a simple signal generator synchronized with a switched capacitor bandpass filter. A general methodology for the use of this structure in the functional verification of a DUT is also provided. The circuit-level design and experimental results of an integrated prototype in standard CMOS 0.5 ?m technology are presented to demonstrate the feasibility of the proposed BIT technique.

A 44-MHz wideband switched-capacitor bandpass filter using double-sampling pseudo-two-path techniques

A fully differential wideband sixth-order switched-capacitor bandpass filter is designed for channel selection in cable TV applications. A modified double-sampling pseudo-two-path technique is proposed to achieve a second-order wideband bandpass filter with a single opamp. Implemented in a standard double-poly four-metal 0.35-/spl mu/m CMOS process and operated at 176-MHz sampling frequency, the filter achieves a measured center frequency of 44 MHz with a bandwidth of 6.28 MHz and a dynamic range of 58.3 dB at 3% IM3. The filter consumes 92.5mW at a single 3.0-V supply and occupies a chip area of 0.52 mm /sup 2/.

A 28-MHz wideband switched-capacitor bandpass filter with transmission zeros for high attenuation

A 28-MHz wideband switched-capacitor (SC) bandpass filter employs an N-path technique and implements transmission zeros in the transfer function to achieve high attenuation. A modified SC biquadratic filter architecture is proposed to achieve high-speed operation. Implemented in a 0.35-/spl mu/m CMOS process, the bandpass filter operates at 28-MHz center frequency with a 3.84-MHz bandwidth and adjacent-channel attenuation of more than 35 dB. At 3-V supply, the filter measures a dynamic range of 37 dB at the 1% THD3 point while dissipating 19.6-mW per pole and occupying a chip area of 1.65 mm/sup 2/.

CMOS RF switched capacitor bandpass filter tuned by ring VCO

A new RF switched capacitor bandpass filter and its command circuit made up of a ring voltage controlled oscillator with ‘XOR’ gates are proposed. Implemented in a standard 0.35 μ m CMOS technology, this circuit is intended to be used in a subset of professional mobile phone applications [380–520 MHz]. Experiments carried out on a prototype show a tunable center frequency range of 260 MHz [240–500 MHz], with a quality factor that can be as high as 300.

New command circuit design for tuning high-Q pseudo 8-path switched-capacitor filter

This paper describes a new association of a high-Q pseudo 8-path switched-capacitor (S-C) bandpass filter and its command circuit made up by a ring VCO with `XOR' gates. The proposed circuit presents the possibility of tuning over a radio-frequency (RF) broadband allowing to sweep different channels with a high quality factor. Designed with CMOS process (0.35µm, for instance), this circuit is intended to replace the surface acoustic wave (SAW) filters in modern wireless receivers. Measurements carried out on a circuit demonstrator show a tunable center frequency range of 200MHz [300-500MHz], with a quality factor higher than 300.

Switched-capacitor bandpass filter with quasi-continuous digital Q-factor tunability

A second-order switched-capacitor (SC) bandpass filter with very wide Q-factor programmability range, is presented. Although the Q-factor is controlled by digitally varying the effective sampling frequency of an SC branch, quasi-continuous programmability is provided. Experimental results from a 0.8 /spl mu/m CMOS integrated prototype demonstrate the versatility of the proposed technique.