Surface Mount Technology Packages Research Articles

Design, materials and process for lead‐free assembly of high‐density packages

The High Density Packaging Users Group conducted a substantial study of the solder joint reliability of high‐density packages using lead‐free solder. The design, material, and assembly process aspects of the project are addressed in this paper. The components studied include many surface mount technology package types, various lead, and printed circuit board finishes and paste‐in‐hole assembly.

Simplification of Finite Element Models for Thermal Fatigue Life Prediction of PBGA Packages

The use of PBGA (plastic ball grid array) electronic packages has been greatly increased in the last decade due to high I/O densities offered. The fatigue life prediction for them is a relatively new task in the electronic field. PBGA packages have more complex geometry than conventional SMT (surface mount technology) packages, such as Leaded and Leadless Chip Carriers (LDCC and LLCC), in which the I/O pins are distributed along the perimeters of chip carriers and their geometries are suitable for two-dimensional (2-D) finite element (FE) simulation. This choice is not so clear in PBGAs. In this study, sectional 2-D, sliced three-dimensional (3-D), and 1/8th 3-D FE models for PBGA assemblies are compared to determine the appropriate FE models that are able to save computational time and memory while maintaining reasonable calculation accuracy. The comparisons and merits of each modeling approach are discussed. An energy-based method is used to predict the fatigue life for solder joints in PBGAs. The fatigue coefficients in the correlation equation, which were obtained previously from the analysis of traditional SMT packages, are updated for more accurate prediction. New fatigue coefficients are obtained for different modeling approaches.

Thermomechanical Finite Element Analysis of Problems in Electronic Packaging Using the Disturbed State Concept: Part 2—Verification and Application

The finite element procedure with the unified disturbed state modeling concept presented in Part I, Basaran et al. (1998), is verified here with respect to laboratory test results for Pb40/Sn60 eutectic solder alloy. This solder alloy is a commonly used interconnection material for surface mount technology packages. It is demonstrated that the proposed procedure provides highly satisfactory correlation with the observed laboratory behavior of materials and with test results for a chip-substrate system simulated in the laboratory.

Finite element simulation of the temperature cycling tests

Temperature cycling tests are commonly used in the semiconductor industry to determine the number of cycles to failure and to predict reliability of the solder joints in the surface mount technology packages. In this paper, the thermomechanical fatigue of Pb40/Sn60 solder joint in a leadless ceramic chip carrier package is studied and temperature cycling test is simulated by using a finite element procedure with the disturbed state concept (DSC) constitutive models. The progress of disturbance (damage) and the energy dissipated in the solder joint during thermal cycling are predicted. It is shown that the disturbance criterion used follows a similar path as the energy dissipation in the system. Moreover, the comparisons between the test data and the finite element analysis show that a finite element procedure using the DSC material models can be instrumental in reliability analysis and to predict the number of cycles to failure of a solder joint. Furthermore, the analysis gives a good picture of the progress of the failure mechanism and the disturbance in the solder joint.