Super Junction Concept Research Articles

Review of technologies for high-voltage integrated circuits

High-Voltage power Integrated Circuits (HVICs) are widely used to realize high-efficiency power conversions (e.g., AC/DC conversion), gate drivers for power devices and LED lighting, and so on. The Bipolar-CMOS-DMOS (BCD) process is proposed to fabricate devices with bipolar, CMOS, and DMOS modes, and thereby realize the single-chip integration of HVICs. The basic integrated technologies of HVICs include High-Voltage (HV) integrated device technology, HV interconnection technology, and isolation technology. The HV integrated device is the core of HVICs. The basic requirements of the HV integrated device are high breakdown voltage, low specific on-resistance, and process compatibility with low-voltage circuits. The REduced SURFace field (RESURF) technology and junction termination technology are developed to optimize the surface field of integration power devices and breakdown voltage. Furthermore, the ENhanced DIelectric layer Field (ENDIF) and REduced BULk Field (REBULF) technologies are proposed to optimize bulk fields. The double/triple RESURF technologies are further developed, and the superjunction concept is introduced to integrated power devices and to reduce the specific on-resistance. This work presents a comprehensive review of these technologies, including the innovation technologies of the authors' group, such as ENDIF and REBULF, substrate termination technology prospective integrated technologies and HVICs in wide band gap semiconductor materials are also discussed.

Improved reverse recovery characteristics obtained in 4H‐SiC double‐trench superjunction MOSFET with an integrated p‐type Schottky diode

A novel double-trench superjunction SiC metal–oxide–semiconductor field-effect transistor (MOSFET) with an integrated Schottky contact at the drain side is proposed in this study. Results indicate an improvement of 58% in reverse recovery current I rrm /charge Q rr and 22% in the trench corner electric field E ox − m compared to the device without Schottky and without superjunction, respectively. This comparison became possible using mixed mode simulations in Sentaurus TCAD. While the improvement in electric field is due to incorporation of superjunction concept along the drift region, the improvement of reverse recovery is due to Schottky contact forming a barrier for the charge carriers. Using calibrated two-dimensional numerical simulations, the authors were able to demonstrate the influence of Schottky contact on reverse recovery current of the device. The superiority of the proposed device is presented by plotting the switching energy loss with respect to external gate resistance and temperature through non-isothermal simulations.

Improved oxide field and switching performance obtained in a CoolSiCTM trench MOSFET by incorporating the superjunction concept

The superjunction concept is incorporated in a CoolSiC trench MOSFET structure to investigate its potential on static and dynamic characteristics using two-dimensional simulations. The effects of device topology on the breakdown voltage and specific on resistance (Rsp,on) are studied. Optimized results show an improvement in the breakdown voltage by 34% and Rsp,on by 30%, compared with the standard CoolSiC MOSFET structure. Furthermore, a marginal improvement in the off state trench corner electric field is obtained. The switching behavior using a clamped inductive circuit showed improved turn on and turn off losses at 900 V, 4 A. After the addition of stray inductance, we observed a less than 0.2 V shift in the gate voltage waveform. Simulation results indicate that the proposed structure has shown improved device characteristics and enhanced turn off performance owing to a reduction in gate charge (Qg) and Miller capacitance.

Superjunction Power Devices, History, Development, and Future Prospects

Superjunction has arguably been the most creative and important concept in the power device field since the introduction of the insulated gate bipolar transistor (IGBT) in the 1980s. It is the only concept known today that has challenged and ultimately proved wrong the well-known theoretical study on the limit of silicon in high-voltage devices. This paper deals with the history, device and process development, and the future prospects of Superjunction technologies. It covers fundamental physics, technological challenges as well as aspects of design and modeling of unipolar devices, such as CoolMOS. The superjunction concept is compared to other methods of enhancing the conductivity of power devices (from bipolar to employment of wide-bandgap materials) to derive its set of benefits and limitations. This paper closes with the application of the superjunction concept to other structures or materials, such as terminations, superjunction IGBTs, or silicon carbide Field Effect Transistors (FETs).

Complete three-dimensional reduced surface field super junction lateral double-diffused metal-oxide-semiconductor field-effect transistor with semi-insulating poly silicon

Lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS) is a key device for the power integrated circuit (PIC) and high voltage integrated circuit (HVIC) technologies. In order to break through the limit relation of 2.5 power between breakdown voltage (BV) and specific on-resistance (Ron,sp) for the traditional LDMOS, and improve the driving capability for the PIC by reducing the power consumption, the new SJ-LDMOS with the semi-insulating poly silicon (SIPOS SJ-LDMOS) is proposed in this paper for the first time, to the best of the authors' knowledge. In order to take full advantage of super junction concept, the SIPOS layer is used for SJ-LDMOS to achieve the effect of the complete three-dimensional reduced surface field (3D-RESURF) for the SJ-LDMOS. The substrate assisted depletion is effectively eliminated by the buffer layer under the super junction. The overall performances of the SIPOS SJ-LDMOS are improved by the uniform and high resistance of the SIPOS layer. The surface electric field is modulated to be uniform by the electric field modulation effect due to the SIPOS layer covering the field oxide. The higher BV would be achieved for the more uniform surface electric field because of the increased average lateral electric field. The BV for the unit length of the drift region is improved to 19.4 V/μupm. The SIPOS SJ-LDMOS along the 3D are subjected to the electric field modulation by the SIPOS layer, which achieves the complete 3D-RESURF effect, thus the drift region with the high concentration can be depleted completely to obtain the high BV. Moreover, in the on-state the majority carrier accumulation can be formed in the drift region of the SIPOS SJ-LDMOS due to the SIPOS layer, so that the specific on-resistance decreases further. In virtue of the ISE simulation, by optimizing the SIPOS layer of the proposed SIPOS SJ-LDMOS, the results show that the specific on-resistance of the SIPOS SJ-LDMOS is 20.87 mΩ·cm2 with a breakdown voltage of 388 V, which is less than 31.14 mΩ·cm2 for the N-buffer SJ-LDMOS with a breakdown voltage of 287 V, and far less than 71.82 mΩ·cm2 for the conventional SJ-LDMOS with a breakdown voltage of only 180 V with the same drift length.

Clustered Insulated Gate Bipolar Transistor in the Super Junction Concept: The SJ-TCIGBT

We report results of comprehensive 2-D simulation evaluation of the first MOS-controlled thyristor structure employing the super junction concept on a 1.2-kV field stop structure. In comparison to a standard device, simultaneous reduction in Vce(sat) and Eoff can be achieved in a super junction trench clustered insulated gate bipolar transistor (SJ-TCIGBT). The simulation results show that up to 80% reduction in Eoff is possible. Unlike the super junction insulated gate bipolar transistors, there is no significant increase in the saturation current with the anode voltage or the depth of the pillars. SJ-TCIGBT is a highly promising next generation device concept with record-breaking Vce(sat)-Eoff tradeoff enhancement to improve converter efficiency.

A Review of Si MOS-gated Power Switches and PiN Rectifiers

Revolutionary advances and developments have been made in power semiconductor device technologies during the last decades which have allowed the improvement of power electronic systems in terms of their efficiency and reliability. The advent of MOS-gated power switches such as the power MOSFET and the IGBT showing high input impedance has been a real breakthrough in the design and fabrication of power electronic systems. This paper reviews the recent progress in the development of Si MOS-gated power devices and rectifiers. The evolution of these devices' technologies together with the introduction of revolutionary device concepts is also discussed. Concretely, the introduction of trench technologies for power MOSFETs and the use of the super-junction concept for breaking the 1D-silicon limit are highlighted. Developments in IGBTs such as those based on the use of thin wafers and strategies for optimising the plasma distribution in PT IGBTs during the on-state are also addressed. Finally, advances in PiN diode technologies including new concepts for both the anode and the cathode structures are also reviewed. These approaches have allowed the reduction of the PiN total losses and a soft reverse recovery behaviour, leading to a more rugged device.

Design and optimization of different P-channel LUDMOS architectures on a 0.18 µm SOI-CMOS technology

This paper focuses on the design and optimization of different power P-channel LDMOS transistors (VBR > 120 V) to be integrated in a new generation of smart-power technology based upon a 0.18 µm SOI-CMOS technology. Different drift architectures have been envisaged in this work with the purpose of optimizing the transistor static (Ron-sp/VBR trade-off) and dynamic (Ron × Qg) characteristics to improve their switching performance. Conventional single-RESURF P-channel LUDMOS architectures on thin-SOI substrates show very poor Ron-sp/VBR trade-off due to their low RESURF effectiveness. Alternative drift configurations such as the addition of an N-type buried layer deep inside the SOI layer or the application of the superjunction concept by alternatively placing stacked P- and N-type pillars could highly improve the RESURF effectiveness and the P-channel device switching performance.

Breaking the theoretical limit of SiC unipolar power device – A simulation study

SiC is known as the next generation material for power semiconductor devices. One important issue in the design of high voltage power devices is the trade-off between breakdown voltage and specific on-resistance. In this paper, possibility of developing 4H–SiC devices beyond its own unipolar theoretical limit R SP _ ON ∝ V BR 2.43 by using the super-junction concept has been investigated for the first time. Effects of structural parameters on the voltage blocking capability and specific on-resistance are studied. Device structures achieving optimum FOMs (Figure of Merit) at various voltage ranges have been designed and their advantages over the conventional structures are quantified. In addition, simple models have also been developed and verified by 2D numerical simulations for 4H–SiC super-junction structures to predict their voltage blocking and forward conduction capability. The results show that, with currently available technology, device FOM (for the same V BR) exceeding the 4H–SiC theoretical unipolar limit by 300% is possible.

SiC Super Junction Power Devices: Modeling and Analysis

In this paper, we extend the super junction concept to SiC high voltage devices and further expand the SiC theoretical limit. It is shown that the super-junction concept can reduce the theoretical specific on-resistance by several times to several orders of magnitude for both silicon and SiC. The unique merit of SiC super-junction devices is that the required P and N pillars have a much smaller aspect ratio and may be easier to form than their silicon counterparts. Furthermore, SiC super-junction devices are much less sensitive to charge imbalance issue than silicon SJ devices.

Oxide-bypassed VDMOS (OBVDMOS): an alternative to superjunction high voltage MOS power devices

The superjunction concept has been proposed to overcome the ideal silicon MOSFET limit, but its fabrication was handicapped by the precise charge balance requirement and inter-diffusion problem. We report a novel device structure termed oxide-bypassed VDMOS (OBVDMOS) that requires the well-established oxide thickness control instead of the difficult doping control in translating the limit to a higher blocking voltage. This is done by using metal-thick-oxide (MTO) at the sidewalls of drift region. One can choose to have a higher blocking voltage or increase the background doping. A PiN structure, essentially identical to MOSFET during off state, was fabricated to demonstrate the proposed concept. Its measured BV/sub dss/ of 170 V is 2.5 times higher than measured conventional device BV/sub dss/ of 67 V on the same silicon wafer.