Sum Of Absolute Difference Calculation Research Articles

FPGA-based stereo matching for crop height measurement using monocular camera

We have proposed a hardware-accelerated drone to analyze the condition of farmland right then and there; as a first step, we report that the proposed system can take crop height measurements with high accuracy using a monocular camera. The proposed three-dimensional farmland is generated using stereo matching, where a drone with a monocular camera can extend the parallax distance as the length between two positions when taking a ground image. This means that our approach can improve the accuracy of a reconstructed 3D farmland. In addition, toward real-time computation and low power consumption, the proposed hardware design accelerates image processing efficiently. Thus, to achieve this, we propose a strategy that combines the semi-global matching (SGM) with single path direction and a sum of absolute difference (SAD) with reduced disparity searching length. For example, a semi-global matching (SGM) was employed to smooth the disparity map result before checking the consistency, where the scan line was performed in one direction, from left to right, to speed up the computation time. The experimental result shows that the computation time performed by Xilinx Zynq ZCU102 FPGA achieves 0.77 s for the stereo data set images with 1536 × 1024 pixels resolution. To meet the real-time application and reduce the FPGA resources toward lower power consumption, the experiment discusses reducing the disparity searching length for the SAD computation. In our experiment, the execution time is less than 40 milliseconds, and the circuit volume is around 9,500 LUTs, equivalent to a small-size FPGA. Finally, we also estimated the object's height; a value of 0.43 m was estimated for the object with a physical height of 0.45 m. Meanwhile, for the object with a physical height of 0.65 m, a value of 0.63 m was estimated.

Analysis of Pel Decimation and Technology Choices to Reduce Energy on SAD Calculation

As the number of pixels per frame tends to increase in new high definition video coding standards such as HEVC and VP9, pel decimation appears as a viable means of increasing the energy efficiency of Sum of Absolute Differences (SAD) calculation. First, we analyze the quality costs of pel decimation using a video coding software. Then we present and evaluate two VLSI architectures to compute the SAD of 4x4 pixel blocks: one that can be configured with 1:1, 2:1 or 4:1 sampling ratios and a non-configurable one, to serve as baseline in comparisons. The architectures were synthesized for 90nm, 65nm and 45nm standard cell libraries assuming both nominal and Low-Vdd/High-Vt (LH) cases for maximum and for a given target throughput. The impacts of both subsampling and LH on delay, power and energy efficiency are analyzed. In a total of 24 syntheses, the 45nm/LH configurable SAD architecture synthesis achieved the highest energy efficiency for target throughput when operating in pel decimation 4:1, spending only 2.05pJ for each 4×4 block. This corresponds to about 13.65 times less energy than the 90nm/nominal configurable architecture operating in full sampling mode and maximum throughput and about 14.77 times less than the 90nm/nominal non-configurable synthesis for target throughput. Aside the improvements achieved by using LH, pel decimation solely was responsible for energy reductions of 40% and 60% when choosing 2:1 and 4:1 subsampling ratios, respectively, in the configurable architecture. Finally, it is shown that the configurable architecture is more energy-efficient than the non-configurable one.

Usage of characteristic points to reduce the time of performance of SAD metric calculation during video flow compression by motion compensation method

Today, it is difficult to imagine a video system that does not use compression of the input video stream for transmission or storage, because the uncompressed size of video files can reach several hundred gigabytes. There are many different video stream compression techniques used in various codecs, however, one of the most commonly used is the motion compensation technique, which allows you to transmit video stream frames in the form of compensated inter frame difference, by finding the motion vectors of individual blocks image. Despite the fact that the above-mentioned technique has been used for the last twenty years, it still has two problem-priority places - assessments of the similarity of image blocks and the algorithm for searching blocks. This article focuses on the problem of estimating the similarity of the image, in order to reduce the time of estimating the similarity of the blocks, which in modern algorithms takes from 40 to 80% of the time of the entire process of encoding the video stream. The article considers the usage of metrics for estimating the similarity of images and their importance for the process of motion compensation during video stream compression, such as SSD (standard deviation) and SAD (sum of absolute differences). The temporal contribution of metrics to the video stream encoding process, in particular to the motion compensation process, is estimated. An algorithm combining classical SAD and parameter estimation based on characteristic points is proposed, which will reduce the metric calculation time for estimating block similarity. The reduction of SAD calculation time due to reduction of comparison points is estimated for three proposed comparison templates - HSAD (half SAD), TSAD (third SAD), DSAD (diagonal SAD). For the selected templates, the results of processing the test video sequence were compared with the results obtained during the processing of the video sequence by the classic SAD. The main attention was paid to the assessment of the following parameters: the relative difference SAD, the increase in the number of candidate blocks, the overlap of candidate blocks.

Energy‐efficient system‐on‐chip reconfigurable architecture design for sum of absolute difference computation in motion estimation process of H.265/HEVC video encoding

SummaryMotion estimation is the important and computationally intensive part of any video encoding. The objective of this paper is to design and analyze the coarse and fine reconfiguration of processing element‐based hardware design for block matching–based motion estimation in H.265/HEVC video processing. Sum of absolute difference (SAD) is the commonly used criteria for block matching in the motion estimation process. User input is taken as the parameter for coarse reconfiguration, and the threshold value in SAD is considered for the fine reconfiguration. Processing elements are the hardware units designed for performing SAD calculation. In this work, the hardware for block‐based motion estimation for H.265/HEVC encoder is designed using multiple processing elements, which will calculate the SAD values. A system‐on‐chip architecture is implemented and verified the optimization in terms of power and area utilization by reconfiguring the architecture dynamically based on the input video quality requirement.

Recongfigurable Hardware-Friendly Early Termination Mechanism in Motion Estimation for HEVC

Motion estimation with a quad-tree variable block size is the driver for the high performance of HEVC in video compression. However, tremendous sum of absolute difference (SAD) computations are needed for every single block size, resulting in huge memory access and power consumption. This work proposes an early termination mechanism at the hardware level that is suitable for quad-tree variable block size motion estimation without degrading video quality. The simulations show reductions in memory access to fetch pixels of about 34.03% and 51.98% saving of SAD computations. This reduction results in reduced power consumption. The simplicity of the algorithm makes it a hardware friendly mechanism, which could be adopted in any motion estimation hardware design.

Pipelined Architecture for Motion Estimation in HEVC Video Coding

Background: High Efficiency Video Coding (HEVC) is the latest video coding standard for video coding. Motion estimation is one of important stages in video coding. In HEVC, the conventional macroblocks are replaced by coding tree units (CTU). Method/Statistical Analysis: The maximum block size is increased from 16×16 to 64×64 in HEVC makes motion estimation more complex. An efficient hardware architecture ha to be designed for real time implementation of motion estimation. In motion estimation, sum of absolute difference (SAD) is calculated between current block and reference blocks present in two different video frames and minimum of SAD gives motion vector of the block. Findings: This paper presents design of pipelined SAD architecture for efficient SAD calculations. The proposed design is used in diamond search algorithm to carry out the motion estimation for evaluating the performance of the design. The proposed architecture employs pipelining at 8×8 block. The proposed design is implemented in TSMC 90 nm technology and operates at maximum frequency of 486 MHz. Applications/Improvements: The design achieves 78% reduction in power compared to the previous design and around 50 % increase in operating frequency.

A low-power VLSI implementation for fast full-search variable block size motion estimation

Variable block size motion estimation (VBSME) is becoming the new coding technique in H.264/AVC. This article presents a low-power VLSI implementation for VBSME, which employs a fast full-search block-matching algorithm to reduce power consumption, while preserving the optimal motion vectors (MVs). The fast full-search algorithm is based on the comparison of the current minimum sum of absolute difference (SAD) to a conservative lower bound so that unnecessary SAD calculations can be eliminated. We first experimentally determine the specific conservative lower bound of SAD and then implement the fast full-search algorithm in FPGA and 0.18 µm CMOS technology. To the best of our knowledge, this is the first time that a fast full-search block-matching algorithm is explored to reduce power consumption in the context of VBSME and implemented in hardware. Experiment results show that the proposed design can save power consumption by 45% compared to conventional VBSME designs that give optimal MV based on the full-search algorithms.

Synthesis and comparison of low-power high-throughput architectures for SAD calculation

Video applications are increasingly present in consumer electronic devices which require low-power and low-energy consumption. Sum of Absolute Differences (SAD) is the most used distortion metric in video coding implementation and consumes a relative large area in the motion estimation hardware. This paper presents the standard-cells synthesis and a comprehensive analysis of various parallel hardware architectures alternatives for SAD calculation, focusing on different design constraints such as high-performance (maximum throughput) and the tradeoff between high-performance and low-power dissipation (namely an isoperformance target). Low-power techniques supported by commercial standard-cells tools are exercised in this design, such as clock gating, multi-threshold (VT) and a combination of slow and fast standard-cells. We achieved significant power reduction for the architectures with lower frequencies and higher parallelism, slow cells and mainly with only one pipeline stage.

Power efficient SDS motion estimation architecture using dynamic iteration control and hierarchical adder compressors for real time HDTV video coding

This paper presents a high performance, power efficient and low hardware cost architecture for motion estimation (ME) targeting portable consumer applications. This hardware uses the Sub-sampled Diamond Search algorithm (SDS) with a Dynamic Iteration Control (DIC). The SDS–DIC algorithm can significantly reduce the number of SAD (Sum of Absolute Difference) calculations for block matching, thus enabling the development of an efficient hardware design for the ME. The DIC technique allows for the required throughput to be achieved with a restriction in the number of iterations, which contributes to the reduction in the overall number of clock cycles needed for the motion vector calculation. The processing units (PU) of the ME were developed by using efficient hierarchical adder-compressors, where simultaneous additions of more than two operands can be performed. The results we present show that, by using both the adder compressors in the PU and the DIC technique, it is possible to obtain an efficient ME architecture with higher performance and reduced power consumption. The architecture that implements this algorithm and the PUs was described in VHDL. Hardware synthesis results are presented for a 0.18 μm CMOS standard cell library. The architecture can reach real time for HDTV 1080p with less than 40 mW of power consumption.

Gradient-based edge detection for motion estimation in H.264/AVC

This study introduces a block-based motion estimation algorithm based on projection with adaptive window-size selection. Using one-dimensional (1D) projection, the original 2D block-matching problem is translated to a simpler 1D matching problem which eliminates the majority of potential pixel participation. The authors propose an efficient fast-motion estimation method using an intensity gradient algorithm to reduce the encoding time. The proposed algorithm estimates the texture direction of the block, and then a horizontal or vertical projection is employed for the sum of absolute difference calculation. Experimental results show that the proposed algorithm achieves a greater than 60% time reduction with negligible peak signal to noise ratio (PSNR) loss and BR increments.

Prediction Error Prioritizing Strategy for Fast Normalized Partial Distortion Motion Estimation Algorithm

A prediction error prioritizing-based normalized partial distortion search algorithm for fast motion estimation is proposed in this letter. The distortion behavior of each pixel in a macroblock is first analyzed to point out the priority/order of sum of absolute difference calculation. Afterward, the normalized partial distortion search algorithm is applied for half-stop of the distortion calculation. In addition, a dynamic search range decision algorithm is adopted for automatically changing the size of the search range to further increase the motion estimation speed. The computational complexity can be reduced significantly through the proposed algorithm, though leaving a PSNR degradation that could be dismissed.

Fast motion estimation based on search range adjustment and matching point decimation

This study introduces a new fast motion estimation (ME) based on both an adaptive search range adjustment and a matching point decimation. In particular, the authors present a maximum matching error constraint in the matching phase that can eliminate an impossible candidate block much earlier than a conventional partial distortion elimination (PDE) scheme. The constraint is computed during the matching error computation based on sum of absolute difference (SAD) between two blocks. The basic idea of the proposed scheme is based on adjusting a given search range adaptively and early eliminating invalid matching blocks effectively. The adaptive search range adjustment is first performed by analysing the contents of a scene. Next, a maximum partial matching error in reordered sub-blocks of an optimal block is obtained, and it is set as a trigger to eliminate invalid blocks for ME. The main contributions of the proposed scheme are that (i) it can reduce a search range adaptively based on the analysis of scene contents; (ii) it can make an early decision for an impossible candidate before complete SAD computation; (iii) the proposed constraint can reduce the computational cost considerably for SAD calculation; and (iv) the proposed matching ideas can be applied to conventional PDE algorithms without significant changes. In order to evaluate the proposed scheme, several baseline approaches are described and compared. The experimental results show that the proposed algorithm can reduce the computational cost more than 86% for ME at the cost of 0.02 dB quality degradation on against the conventional PDE algorithm.

Hardware-Oriented Early Detection Algorithms for 4*4 and 8*8 All-Zero Blocks in H.264

H.264 is the latest HDTV video compression standard, which provides a significant improvement in coding efficiency at the cost of huge computation complexity. After transform and quantization, if all the coefficients of the block's residue data are zero, this block is called all-zero block (AZB). Provided that an AZB can be detected early, the process of transform and quantization on an AZB can be skipped, which reduces significant redundant computations. In this paper, a theoretical analysis is performed for the sufficient condition for AZB detection. As a result, a partial sum of absolute difference (SAD) based 4 × 4 AZB detection algorithm is derived. And then, a hardware-oriented AZB detection algorithm is proposed by modifying the order of SAD calculation. Furthermore, a quantization parameter (QP) oriented 8 × 8 AZB detection algorithm is proposed according to the AZB's statistical analysis. Experimental results show that the proposed algorithm outperforms the previous methods in all cases and achieves major improvement of computation reduction in the range from 6.7% to 42.3% for 4 × 4 blocks, from 0.24% to 79.48% for 8 × 8 blocks. The computation reduction increases as QP increases.

Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling

This paper presents a processor architecture for high-speed and reliable tinocular stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and-pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on regularity of reference pixels. The stereo matching processor is designed in a 0.18μm CMOS technology. The processing time is 83.2μs@100MHz. By using optimal scheduling, the increases in area and processing time is only 5% and 3% respectively compared to binocular stereo vision although the computational amount is double.

Binary Motion Estimation with Hybrid Distortion Measure

This paper proposes a new binary motion estimation algorithm that improves the motion vector accuracy by using a hybrid distortion measure. Unlike conventional binary motion estimation algorithms, the proposed algorithm considers the sum of absolute difference (SAD) as well as the sum of bit-wise difference (SBD) as a block-matching criterion. In order to reduce the computational complexity and remove additional memory accesses, a new scheme is used for SAD calculation. This scheme uses 8-bit data of the lowest layer already moved into the local buffer to calculate the SAD of other higher binary layer. Experimental results show that the proposed algorithm finds more accurate motion vectors and removes the blockishness of the reconstructed video effectively. We applied this algorithm to existing video encoder and obtained noticeable visual quality enhancement.

Fast Variable Block Size Motion Estimation by Adaptive Early Termination

This paper presents a fast motion estimation algorithm by adaptively changing the early termination threshold for the current accumulated partial sum of absolute difference (SAD) value. The simulation results show that the proposed algorithm can provide the similar quality while saving 77.9% and 50.6% of SAD computation when comparing with early termination methods in MPEG-4 VM18.0 and H.264 JM9.0, respectively.

SAD computation based on online arithmetic for motion estimation

Block-based motion estimation is one of the critical tasks in today's video compression standards such as H.26x, MPEG-1, -2 and -4. Most of the block-based motion estimation algorithms are based on computing the sum of absolute differences (SAD) between corresponding elements in the candidate and reference blocks. In this paper, an field-programmable gate-array (FPGA) design is proposed for rapidly computing the minimum SAD. Two goals are achieved due to the use of online arithmetic (OLA): it is possible to implement a full 16×16 macroblock SAD in a single FPGA device; and it allows us to speed up computation by early termination of the SAD calculation when the candidate involved is bigger than the current reference SAD. Reconfigurable devices enable us to change 8×8 or 16×16 pixels per block quickly and easily. For a 16×16 SAD unit 1945 look-up tables (LUTs) are required at 425 MHz. A comparison with other related works is provided.

FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture

This paper presents a processor architecture for high-speed and reliable stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and-pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on the regularity of reference pixels. The stereo matching processor is implemented on an FPGA. Its performance is 80 times higher than that of a microprocessor ([email protected] GHz), and is enough to generate a 3-D depth image at the video rate of 33 MHz.

Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access

This paper presents a VLSI processor for high-speed and reliable stereo matching based on adaptive window-size control of SAD(Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using multi-resolution images. Parallel memory access is essential for highly parallel image processing. For parallel memory access, this paper also presents an optimal memory allocation that minimizes the hardware amount under the condition of parallel memory access at specified resolutions.

Global Elimination Algorithm and Architecture Design for Fast Block Matching Motion Estimation

This paper presents a new block matching motion estimation algorithm and its VLSI architecture design. The proposed global elimination algorithm (GEA) was derived from successive elimination algorithm (SEA), which can skip unnecessary sum of absolute difference (SAD) calculation by comparing minimum SAD with subsampled SAD (SSAD). Our basic idea is to separate the decision of early termination and SAD calculation for each candidate block to make data flow more regular and suitable for hardware. In short, we first compare the rough characteristics of all candidate blocks with the current block (SSAD). In turn, we select several best roughly matched candidate blocks to re-compare them with the current block by using detailed characteristics (SAD). Other features of GEA include fixed processing cycles, no initial guess, and high video quality (almost the same as full search). Unlike other fast algorithms, the mapping of GEA to hardware is very simple. We proposed an architecture that is composed of a systolic part to efficiently compute SSAD, an adder tree to support both SSAD and SAD calculations, and a comparator tree to avoid expensive sorting circuits. Simulation results show that our design is much more area efficient than many full-search architectures while maintaining high video quality and processing capability.