Successive Cancellation Decoding Of Polar Codes Research Articles

Fast Successive-Cancellation Decoding of Polar Codes With Sequence Nodes

Fast Successive-Cancellation Decoding of Polar Codes With Sequence Nodes

Generalized Constituent Nodes for Simplified Successive-Cancellation Decoding of Multi-Kernel Polar Codes

The decoding latency of the successive-cancellation decoder for polar codes is of great importance in its practical applications, and it can be reduced by implementing multi-bit decision decoders in the constituent nodes of the decoding tree. In this letter, we develop a matrix analysis method to analyze the corresponding parity submatrix of the decoding tree’s internal node. Two generalized constituent nodes are presented for the fast simplified successive-cancellation (fast-SSC) decoding of linear kernels-mixed multi-kernel polar codes. Results show that the proposed method achieves latency reduction and preserves the error-correction performance.

Simulated Annealing Algorithm-Aided SC Decoder for Polar Codes

A new decoding scheme aided by simulated annealing algorithm is proposed to further improve the decoding performance of successive cancellation (SC) for polar codes at the short block. We use simulated annealing to revise the decoding result of SC which cannot pass the CRC check. To generate the new neighbors, the decoder flips one bit from the set of the least unreliable information bits each time in the estimated source vector of SC decoding. Euclidean distance is used to measure the gap between the new neighbor solution and the received word so that the decoder can obtain a global optimal solution. Simulation shows that the proposed decoder has a performance gain about 0.5 dB in terms of frame error rate (FER) under short blocks in the additive white Gaussian noise (AWGN) channel compared to other basic decoders, while keeping a low time cost through a parameter tuning process.

Parallelism Versus Latency in Simplified Successive-Cancellation Decoding of Polar Codes

This paper characterizes the latency of the simplified successive-cancellation (SSC) decoding scheme for polar codes under hardware resource constraints. In particular, when the number of processing elements P that can perform SSC decoding operations in parallel is limited, as is the case in practice, the latency of SSC decoding is O(N1-1/μ + N/P log2 log2 N/P), where N is the block length of the code and μ is the scaling exponent of the channel. Three direct consequences of this bound are presented. First, in a fully-parallel implementation where P = N/2, the latency of SSC decoding is O(N1-1/μ), which is sublinear in the block length. This recovers a result from our earlier work. Second, in a fully-serial implementation where P = 1, the latency of SSC decoding scales as O(N log2 log2 N). The multiplicative constant is also calculated: we show that the latency of SSC decoding when P = 1 is given by (2 + o(1))N log2 log2 N. Third, in a semi-parallel implementation, the smallest P that gives the same latency as that of the fully-parallel implementation is P = N1/μ. The tightness of our bound on SSC decoding latency and the applicability of the foregoing results is validated through extensive simulations.

Threshold-Based Fast Successive-Cancellation Decoding of Polar Codes

Fast SC decoding overcomes the latency caused by the serial nature of the SC decoding by identifying new nodes in the upper levels of the SC decoding tree and implementing their fast parallel decoders. In this work, we first present a novel sequence repetition node corresponding to a particular class of bit sequences. Most existing special node types are special cases of the proposed sequence repetition node. Then, a fast parallel decoder is proposed for this class of node. To further speed up the decoding process of general nodes outside this class, a threshold-based hard-decision-aided scheme is introduced. The threshold value that guarantees a given error-correction performance in the proposed scheme is derived theoretically. Analysis and hardware implementation results on a polar code of length 1024 with code rates 1/4, 1/2, and 3/4 show that our proposed algorithm reduces the required clock cycles by up to 8%, and leads to a 10% improvement in the maximum operating frequency compared to state-of-the-art decoders without tangibly altering the error-correction performance. In addition, using the proposed threshold-based hard-decision-aided scheme, the decoding latency can be further reduced by 57% at E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sub> /N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> = 5.0 dB.

Reduced Complexity Successive-Cancellation Decoding of Polar Codes Based on Linear Approximation

Reduced Complexity Successive-Cancellation Decoding of Polar Codes Based on Linear Approximation

A High-Speed Successive-Cancellation Decoder for Polar Codes Using Approximate Computing

Polar codes are a new class of forward-error-correction codes, which have been proved asymptotically capacity-achieving for symmetric memoryless channels. Successive-cancellation (SC) decoders are low complexity while suffering from low speed due to their serial processing nature. Based on a newly published fast simplified SC algorithm, we propose a more efficient decoder than the prior art in this brief. Well-optimized components in the decoder core are developed. Additionally, several efficient approximate computing units (Apx-CUs) are introduced to substitute their accurate counterparts in the decoder to achieve even higher operating frequency. Field-programmable gate-array implementation results show that our design is about 1.5 times faster than the prior art, and the proposed Apx-CUs can bring an additional 19% processing speed.

Improvement of Fast Simplified Successive-Cancellation Decoder for Polar Codes

This paper presents a new latency reduction method for successive-cancellation (SC) decoding of polar codes that performs a frozen-bit checking on the rate-other (R-other) nodes of the Fast Simplified SC (Fast-SSC) pruning tree. The proposed method integrates the Fast-SSC algorithm and the Improved SSC method (frozen-bit checking of the R-other nodes). We apply a recognition-based method to search for as many constituent codes as possible in the decoding tree offline. During decoding, the current node can be decoded directly, if it is a special constituent code; otherwise, the frozen-bit check is executed. If the frozen-bit check condition is satisfied, the operation of the R-other node is the same as that of the rate-one node. In this paper, we prove that the frame error rate (FER) performance of the proposed algorithm is consistent with that of the original SC algorithm. Simulation results show that the proportion of R-other nodes that satisfy the frozen-bit check condition increases with the signal-to-noise-ratio (SNR). Importantly, our proposed method yields a significant reduction in latency compared to those given by existing latency reduction methods. The proposed method solves the problem of high latency for the Improved-SSC method at a high code rate and low SNR, simultaneously.

Efficient Partial-Sum Network Architectures for List Successive-Cancellation Decoding of Polar Codes

List successive cancellation decoder (LSCD) architectures have been recently proposed for the decoding of polar codes to achieve high decoding performance. However, the existing architectures for updating the partial sums of all the list candidate paths scale linearly with the code length and hence have significant area and delay overhead for polar codes with long code length or list size. In this paper, a list high-performance partial-sum network (LHPPSN) is proposed based on a folded partial-sum network (PSN) architecture of which the complexity does not scale with the code length. A design based on replicating units of high-performance PSN and lazy copying is first presented. To improve the area and performance, a new method based on indices copying is proposed next. In addition, by exploiting the properties of PSN, the complexity is further reduced by sharing the path copying logic. Experimental results show that using the proposed LHPPSN results in more than 70% and 40% reduction in area and delay, respectively, for polar codes with large code length or list size, when compared with the state-of-the-art LSCD PSN architectures.

LLR-Based SC Decoding of Polar Codes for Two-User Binary-Input MAC

This letter considers a hardware-friendly log-likelihood ratio (LLR)-based successive cancellation (SC) decoding of polar codes for two-user binary-input multiple access channels. Based on the known recursive equations in the likelihood domain, we obtain LLR-based recursive equations for the SC decoding. An approximate LLR-based decoding is also introduced, which shows small performance loss at high error rate, but has significantly low complexity compared with the previous likelihood-based decoding.

Simplified Successive Cancellation Decoding of Polar Codes With Medium-Dimensional Binary Kernels

A method is proposed, called $l$ -formula, to design efficient successive cancellation (SC) decoding of polar codes with medium-dimensional binary kernels (dimensions up to 16). Our $l$ -formula method obtains the simplified recursive formulas of the SC decoder in the likelihood ratio domain for any binary kernel. We confirm that the complexity of the SC decoder based on $l$ -formulas achieves considerable advantages over the straightforward SC decoder for polar codes with medium-dimensional binary kernels.

Improved Successive-Cancellation Decoding of Polar Codes Based on Recursive Syndrome Decomposition

In this letter an improved method for the successive-cancellation decoding of polar codes is proposed. To avoid computations associated with redundant tree-traversals and syndrome calculations, recursive properties of polar codes are newly exploited in the proposed algorithm. Instead of computing a syndrome vector at every node, some syndrome vectors are directly obtained by recursively decomposing the syndrome vector computed previously. Furthermore, a modified syndrome check rule is proposed to prune unnecessary sub-trees efficiently. Compared with the latest pruning method, the proposed method reduces the latency by 23% for a (2048, 1024) polar code without sacrificing the error-correcting performance.

Fast Successive-Cancellation Decoding of Polar Codes: Identification and Decoding of New Nodes

The decoding latency of polar codes can be reduced by implementing fast parallel decoders in the last stages of decoding. In this letter, we present five such decoders corresponding to different frozen-bit sequences to improve the decoding speed of polar codes. Implementing them achieves significant latency reduction without tangibly altering the bit-error-rate performance of the code.

Efficient Pruning for Successive-Cancellation Decoding of Polar Codes

This letter presents an efficient pruning method for the successive-cancellation (SC) decoding of polar codes. In the proposed method, unnecessary sub-trees are pruned if the syndrome check of a constituent code is satisfied. Without sacrificing the error-rate performance, the recursive operation associated with such a constituent code is replaced with simple computations. Compared with the traditional SC decoding, the proposed pruning decreases the decoding latency by 85% on the average for the polar (1024, 512) code.

An Improvement of Modified Successive-Cancellation Decoder for Polar Codes

An improvement is introduced of the modified successive-cancellation (MSC) decoding for polar codes, in which local decoders at rate-other nodes are simplified. This improvement reduces the decoding latency and complexity of the MSC decoding with no sacrifice in error performance. Furthermore, in our method, the decoding latency decreases rapidly with increasing signal-to-noise ratio. Significant latency and complexity reductions are shown by simulation results.

A Scalable Successive-Cancellation Decoder for Polar Codes

Polar codes, discovered by Ar{\i}kan, are the first error-correcting codes with an explicit construction to provably achieve channel capacity, asymptotically. However, their error-correction performance at finite lengths tends to be lower than existing capacity-approaching schemes. Using the successive-cancellation algorithm, polar decoders can be designed for very long codes, with low hardware complexity, leveraging the regular structure of such codes. We present an architecture and an implementation of a scalable hardware decoder based on this algorithm. This design is shown to scale to code lengths of up to N = 2^20 on an Altera Stratix IV FPGA, limited almost exclusively by the amount of available SRAM.

A Semi-Parallel Successive-Cancellation Decoder for Polar Codes

Polar codes are a recently discovered family of capacity-achieving codes that are seen as a major breakthrough in coding theory. Motivated by the recent rapid progress in the theory of polar codes, we propose a semi-parallel architecture for the implementation of successive cancellation decoding. We take advantage of the recursive structure of polar codes to make efficient use of processing resources. The derived architecture has a very low processing complexity while the memory complexity remains similar to that of previous architectures. This drastic reduction in processing complexity allows very large polar code decoders to be implemented in hardware. An N=217 polar code successive cancellation decoder is implemented in an FPGA. We also report synthesis results for ASIC.

A Simplified Successive-Cancellation Decoder for Polar Codes

A modification is introduced of the successive-cancellation decoder for polar codes, in which local decoders for rate-one constituent codes are simplified. This modification reduces the decoding latency and algorithmic complexity of the conventional decoder, while preserving the bit and block error rate. Significant latency and complexity reductions are achieved over a wide range of code rates.