Subthreshold Supply Voltages Research Articles

Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application

The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm Complementary Metal-Oxide Semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when compared with Fin Field-Effect Transistor (FinFET) device. The leakage current is more in CMOS devices while in FinFET device due to the control of multi-Gates on the channel, the leakage current is reduced. This will improve the power consumption in the FinFET device when compared to CMOS devices. The comparator results shows that CMOS device is inferior when compared with FinFET device comparator. For the implementation of the comparator Spice model were used in this work. The software used in the project is synopsis Hspice.

0.3-V $RC$ -to-Digital Converter Using a Negative Charge-Pump Switch

This brief proposes a 0.3-V resistance and capacitance-to-digital converter (RCDC) using a negative charge-pump switch. The proposed RCDC operates at a subthreshold supply voltage by using the negative charge-pump switch, which turns on a precharge pMOS switch with a negative supply voltage. It converts resistance or capacitance to digital signals. The proposed RCDC was fabricated using a 65-nm CMOS process. It achieves ENOBs of 10.6 bits for the resistance of 1–100k $\Omega $ and the capacitance of 10 pF–10 nF, which correspond to figure-of-merits (FoMs) of 3.03 pJ/step and 2.54 pJ/step, respectively, at the supply voltage of 0.3 V.

An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications

Energy consumption is a key issue in portable biomedical devices that require uninterrupted biomedical data processing. As the battery life is critical for the user, these devices impose stringent energy constraints on SRAMs and other system on chip (SoC) components. Prior work shows that operating CMOS circuits at subthreshold supply voltages minimizes energy per operation. However, at subthreshold voltages, SRAM bitcells are sensitive to device variations, and conventional 6T SRAM bitcell is highly vulnerable to readability related errors in subthreshold operation due to lower read static noise margin (RSNM) and half-select issue problems. There are many robust subthreshold bitcells proposed in the literature that have some improvements in RSNM, write static noise margin (WSNM), leakage current, dynamic energy, and other metrics. In this paper, we compare our proposed bitcell with the state of the art subthreshold bitcells across various SRAM design knobs and show their trade-offs in a column mux scenario from the energy and delay metrics and the energy per operation metric standpoint. Our 9T half-select-free subthreshold bitcell has 2.05× lower mean read energy, 1.12× lower mean write energy, and 1.28× lower mean leakage current than conventional 8T bitcells at the TT_0.4V_27C corner. Our bitcell also supports the bitline interleaving technique that can cope with soft errors.

Single-ended, robust 8T SRAM cell for low-voltage operation

Recently, an SRAM has been in the development stage, with its objective to withstand the ever-increasing process variations as well as to support ultra-low power applications, even at subthreshold supply voltages. In this paper, a new 8T SRAM cell, which employs a single bitline scheme to perform the write and read operations, is proposed. This scheme enhances the write ability and read stability by cutting off the feedback loop of the inverter pair, thereby eliminating the read and write constraints on the transistor dimensions. Additionally, it efficiently trims down the write power and standby power consumption. The experimental results show that the proposed 8T cell achieves 4.66× write ability, 2.33× read noise margin, 28.0% write power reduction, and 3.3× lower standby power dissipation when compared with a 6T bit-cell at 0.5V through a Monte Carlo simulation (10,000 times) using the TSMC 65-nm process. Moreover, it also achieves higher process variation tolerance at an ultralow operating voltage.

A Robust SRAM Design for Ultra Dynamic Voltage Scalable VLSI System

In this paper, a SRAM array targeting IBM 130nm CMOS technology is proposed for ultra dynamic voltage scaling (UDVS) application with better immunity against process variation. A type of modified Schmitt Trigger inverter is adopted in the SRAM design, which guarantee stable operations in both superthreshold and subthreshold supply voltage regions. Testing results demonstrate that the proposed SRAM array functions well in the supply voltage range of 150 mV to 1200 mV. The optimum-energy supply voltage point is about 400 mV for proposed UDVS SRAM array. And the energy at 400 mV decreases by 62.5% compared to that at 1200 mV.

Comparative Analysis of SEU in FinFET SRAM Cells for Superthreshold and Subthreshold Supply Voltage Operation

Subthreshold circuits are extensively used to reduce power consumption. However, increased susceptibility to radiation particles strikes can significantly impact the reliability of such systems. In this brief, we analyze different FinFET static-random-access-memory (SRAM) cells for single-event-upset immunity and compare their performance when operated with superthreshold and subthreshold supply voltage. Based on these observations, we propose several guidelines for radiation hardening of subthreshold FinFET SRAM designs. These guidelines suggest that the traditional radiation-hardening approaches need to be revisited for subthreshold designs.

P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation

SRAM has been under its renovation stage recently, aiming to withstand the ever-increasing process variation as well as to support ultra-low-power applications using even subthreshold supply voltages. We present in this paper a novel P-P-N-based 10T SRAM cell, in which the latch is formed essentially by a cross-coupled P-P-N inverter pair. This type of cell can operate at a voltage as low as 285 mV while still demonstrating high resilience to process variation. Its noise margin has been elevated in not only the hold state, but also the read operations. As compared to previous 10T SRAM cells, our cell excels in particular in two aspects: 1) ultra-low cell leakage, and 2) high immunity to the data-dependent bitline leakage. The second merit makes it especially suitable for an SRAM macro with long bitlines - a property often desirable in order to achieve high density. We have fabricated and validated its performance through a 16 Kb SRAM test chip using the UMC 90 nm process technology.

A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing

The access timing control of low-voltage static random access memory cells encounters crucial challenges in the presence of within-die (WID) variations, which induce severe delay mismatches between the timing-reference circuit and the bitlines. Prevention of early activation of sense amplifiers (SAs) is thus required to improve the yield. This brief proposes a novel SA-activation scheme by sensing differential bitlines locally and concurrently. The proposed structure effectively tolerates the WID variations and supports dynamic voltage scaling down to the subthreshold supply voltage. Measurement results show that the fabricated 8-kb test chips using 90-nm technology can be operated at the supply voltage range from 1 V (nominal V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> ) to 0.16 V. The maximum operating frequency at 0.16 V is up to 200 kHz.

A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V$_{\min}$ Lowering Techniques and Deep Sleep Mode

A voltage scalable 0.26 V, 64 kb 8T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process. Utilization of the reverse short channel effect in a SRAM cell design improves cell write margin and read performance without the aid of peripheral circuits. A marginal bitline leakage compensation (MBLC) scheme compensates for the bitline leakage current which becomes comparable to a read current at subthreshold supply voltages. The MBLC allows us to lower Vmin to 0.26 V and also eliminates the need for precharged read bitlines. A floating read bitline and write bitline scheme reduces the leakage power consumption. A deep sleep mode minimizes the standby leakage power consumption without compromising the hold mode cell stability. Finally, an automatic wordline pulse width control circuit tracks PVT variations and shuts off the bitline leakage current upon completion of a read operation.

Techniques to Extend Canary-Based Standby $V_{DD}$ Scaling for SRAMs to 45 nm and Beyond

<i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VDD</i> scaling is an efficient technique to reduce SRAM leakage power during standby mode. The data retention voltage (DRV) defines the minimum <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VDD</i> that can be applied to an SRAM cell without losing data. The conventional worst-case guard-banding approach selects a fixed standby supply voltage at design time to accommodate the variability of DRV, which sacrifices potential power savings for non-worst-case scenarios. We have proposed a canary-based feedback to achieve aggressive power savings by tracking PVT variations through canary cell failures. In this paper, we show new measured silicon results that confirm the ability of the canary scheme to track PVT changes. We thoroughly analyze the adaptiveness of the canary cells for tracking changes in the SRAM array, including the ability to track PVT fluctuations. We present circuits for robustly building the control logic that implements the feedback mechanism at subthreshold supply voltages, and we derive a new analytical model to help tune the canary cells in the presence of variations. To realistically quantify the potential savings achievable by the canary scheme, we assess the impact of various sources of overhead. Finally, we investigate the performance of the canary based scheme in nanometer technologies, and we show that it promises to provide substantial standby power savings down to the 22 nm node.

The limit of dynamic voltage scaling and insomniac dynamic voltage scaling

Dynamic scaling (DVS) is a popular approach for energy reduction of integrated circuits. Current processors that use DVS typically have an operating range from full to half of the maximum V/sub dd/. However, there is no fundamental reason why designs cannot operate over a much larger range: from full V/sub dd/ to subthreshold voltages. This possibility raises the question of whether a larger range improves the energy efficiency of DVS. First, from a theoretical point of view, we show that, for subthreshold supply voltages, leakage energy becomes dominant, making just-in-time computation energy-inefficient at extremely low voltages. Hence, we introduce the existence of a so-called voltage which is the at which the application is executed with the highest possible energy efficiency and below which scaling reduces energy efficiency. We derive an analytical model for the energy-optimal and study its trends with technology scaling and different application loads. Second, we compare several different low-power approaches including MTCMOS, standard DVS, and the proposed Insomniac (extended DVS into subthreshold operation). A study of real applications on commercial processors shows that Insomniac provides the best energy efficiency. From these results, we conclude that extending the range below V/sub dd//2 will improve the energy efficiency for many processor designs.