Subthreshold MOS Transistors Research Articles

A 0.9-V 33.7-ppm/°C 85-nW Sub-Bandgap Voltage Reference Consisting of Subthreshold MOSFETs and Single BJT

A low temperature coefficient (TC) and high power supply ripple rejection (PSRR) CMOS sub-bandgap voltage reference (sub-BGR) circuit using subthreshold MOS transistors and a single BJT is presented in this brief. The proposed sub-BGR consists of a novel complementary-to-absolute-temperature (CTAT) voltage generator based on a scaled emitter-base voltage of a BJT, and an improved proportional-to-absolute-temperature (PTAT) voltage generator based on stacking of $\Delta V_{\mathbf {GS}}$ of sub- $V_{\mathbf {TH}}$ MOSFETs. As the CTAT circuit achieves a reduced absolute value of the negative TC, the PTAT circuit achieves reduced power consumption without consuming a large chip area. The proposed sub-BGR circuit is implemented in a standard 0.18- $\mu \text{m}$ CMOS process. Measured results show that the sub-BGR circuit can run with a supply voltage down to 0.9 V while the power consumption is only 85 nW. An average TC of 33.7 ppm/°C and a PSRR of better than −40 dB over the full frequency range are achieved.

A Time-Mode Translinear Principle for Nonlinear Analog Computation

This work proposes a novel translinear principle based on time domain processing of signals. The exponential relationship between voltage and time in an RC circuit is exploited to implement a logarithmic voltage-to-time converter and an exponential time-to-voltage converter. These circuits are the time domain analogs of the voltage mode translinear circuits that exploit the exponential relationship between current and voltage in BJTs and subthreshold MOS transistors. Just as Kirchoff's voltage laws provide a natural form of addition for the voltage-mode translinear principle, the progression of time can also be a natural source of addition for the proposed time-mode analog of this principle. In this work a time-mode adder circuit is used to realize a translinear principle in time. This paper describes the theory behind this time-mode translinear principle. Furthermore, the design of nonlinear circuit functions, e.g., multiplication and power law, based on the time-mode translinear principle is described. Simulation and measurement results for a two-input single quadrant multiplier are presented. The chip was fabricated in a 180 nm CMOS process with simulation results agreeing closely with experimental results. We also present error analysis for such circuits and provide a brief discussion on future prospects of this approach.

A general translinear principle for subthreshold MOS transistors

This paper revises the conditions under which the translinear principle can be fully exploited for MOS transistors operating in subthreshold. Due to the exponential nature of subthreshold MOS transistors, the translinear principle applies immediately as long as the source-to-bulk voltages are made equal to zero (or constant). This paper addresses the conditions under which subthreshold MOS transistors still satisfy a translinear principle, but without imposing this constraint on all V/sub BS/ voltages. It is found that the translinear principle results in a more general formulation than the originally found for BJT's since now multiple translinear loops can be involved. The constraint of an even number of transistors is no longer necessary. Some corollaries are stated as well and, finally, it is shown how to use the theorem for subthreshold MOS transistors operated in the ohmic regime.

A subthreshold MOS circuit for the Lotka–Volterra neural network producing the winners-share-all solution

An analog MOS circuit is proposed for implementing a Lotka–Volterra (LV) competitive neural network which produces winners-share-all solutions. The solutions give multiple winners receiving large inputs and are particularly useful for selecting a set of inputs through “decision by majority”. We show that the LV network can easily be implemented using subthreshold MOS transistors. Results of extensive circuit simulations prove that the proposed circuit does exhibit a reliable selection compared with winner-take-all circuits, in the possible presence of device mismatches. These results pave a way to future implementation on a real device.

Proposal for an implementation of reversible gates in c-MOS

Abstract A method is given for designing reversible logic circuits with the help of subthreshold complementary MOS transistors. Successively, implementations of the reversible inverter and a reversible logic gate, similar to the notorious Fredkin gate, are introduced. As any boolean computer can be built from these two building blocks, this implies that any combinatorial computer can thus be designed. The resulting machine will be able to calculate in both directions, such that input and output are indistinguishable.