Substrate Noise Reduction Research Articles

RF characterization of the substrate coupling noise between TSV and active devices in 3D integrated circuits

3D technology (TSVs, RDL, copper pillars) is gaining more and more interest. The functionalities and performances of the Wide I/O prototype (memory on logic 3D IC), developed by ST, ST-Ericson and CEA-LETI, was fully demonstrated. 3D process is mature enough to address next applications such as radiofrequency, analogic, and photonics. Nevertheless new challenges appear when 3D technology and these applications meet together. Particularly the parasitic electrical coupling of the TSV with active devices is a matter of interest and is investigated in this paper.Considering that the TSV will be a connection for several applications, characterized by a wide frequency domain, the signal transmission could generate substrate noise impacting MOS circuit operations. Noise coupling between TSV and active areas has to be characterized on a wide frequency range. The extraction of this coupling factor in the complex 3D circuit environment represents the bigger challenge of this study.An original strategy is proposed to investigate the coupling between TSVs and the complex MOS structure, consisting in splitting up the MOS into elementary wells with adequate doping conditions. It entailed innovative test structure design and definition of characterization method with RF and DC sources. The TSV under test is near different MOS wells and the noise coupling transfer factors were measured from 10MHz to 40GHz. They exhibit wide variations, increasing with frequency, from minimum −55dB to maximum −25dB. Variations according to the well implant and its applied polarization is also observed. It is explained by the presence of p-n junctions which is in agreement with an equivalent electrical model of structure.The sensitivity to substrate noise of PMOS and NMOS wells, standing for drain, source and bulk plug, were characterized and compared. TSV coupling with PMOS device is expected to be more critical than with NMOS. P+ plug is shown to be an efficient solution for substrate noise reduction.

Characterization of TSV-Induced Loss and Substrate Noise Coupling in Advanced Three-Dimensional CMOS SOI Technology

Electrical loss and substrate noise coupling induced by through-silicon-vias (TSVs) in silicon-on-insulator (SOI) substrates is characterized in frequency and time domains. A three-dimensional (3-D) test site in 45-nm CMOS SOI including copper-filled TSVs and microbumps ( μC4's) is fabricated and measured to extract the interconnect loss. Good correlation to the electrical circuit models is demonstrated up to 40 GHz. In addition to a buried oxide layer, a highly doped N+ epilayer used for deep trench devices in 22-nm CMOS SOI is considered in full-wave electromagnetic simulations. Equivalent circuit models are extracted to assess the impact of noise coupling on active circuit performance. A noise mitigation technique of using CMOS process compatible buried interface contacts is proposed and studied. Simulation results demonstrate that a low-impedance ground return path can be readily created for effective substrate noise reduction in 3-D IC design.

Substrate Noise Coupling Reduction in $LC$ Voltage-Controlled Oscillators

In this letter, a substrate noise coupling effect in LC voltage-controlled oscillators (VCOs) was investigated. By 0.18-mum CMOS technology, three 2.4-GHz VCOs were designed using different types of spiral inductors to observe the substrate noise induced spurs. Compared with the design using a standard inductor, the proposed deep N-well (DNW) and patterned ground shield (PGS) VCOs demonstrated clearly reduced third-order intermodulation spurs by 6-8 and 10-15 dB, respectively. Based on the established physical-based equivalent circuit models, we found that the low-impedance paths introduced by DNW and PGS were the dominant factor for the observed substrate noise reduction in the proposed VCOs.

Self‐Aligned Wafer‐Level Integration Technology with an embedded faraday cage for substrate crosstalk suppression

AbstractA modification to a recently developed chip/wafer integration technology has proven to be very effective in suppressing the substrate crosstalk for mixed signal systems. In this implementation, analog and digital chips are fabricated on separate dies, and then integrated on a single Si substrate using a Self‐Aligned Wafer‐Level Integration Technology. A truly grounded faraday‐cage structure is realized by sidewall metallization around each die resulting in an ultimate substrate noise reduction. Any planar chip with any thickness can be used in this technology. Simulation and measurement results show that when a high‐resistivity silicon substrate as an integration medium is used along with grounded faraday cage, substrate coupling is suppressed to less than −60 dB for frequencies up to 25 GHz. For a low‐resistivity silicon substrate, the substrate coupling is a dominant mechanism in generating mixed‐signal noise, however, when sidewall metallization as faraday cage is utilized, the substrate coupling is reduced by at least 20 dB for frequencies below 25 GHz. The substrate noise suppression is higher than 35 dB for frequencies below 2 GHz. To our knowledge, these are the best values reported for isolation improvement of thick silicon substrates at microwave frequencies. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 829–832, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23207

Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply

SUMMARY This paper demonstrates a feedforward active substrate noise cancelling technique using a power supply di/dt detector. Since the substrate is usually tied with the ground line with a low impedance, the substrate noise is closely related to the ground bounce which is proportional to the di/dt when inductance is dominant on the ground line impedance. Our active cancelling detects the di/dt of the power supply, and injects an anti-phase current into the substrate so that the di/dt-proportional substrate noise is cancelled out. Our first trial shows that 34% substrate noise reduction is achieved on our test circuit, and the theoretical analysis shows that the optimized canceller design will enhance the substrate noise suppression ratio up to 56%.

EVALUATION OF TECHNOLOGY OPTIONS FOR SUBSTRATE NOISE REDUCTION

Substrate coupling is a phenomenon that affects the behavior and performance of RF and mixed signal ICs. Prediction of such crosstalk during the design process can help designers. In this paper, a new methodology is presented for performing a fast and reliable characterization of the noise transmission path, modeling the substrate as a resistive network. Adopting only DC measurement techniques, the dependence of disturbances attenuation on the geometric parameters is found. Moreover, the relation between attenuation and disturbance types is indicated. Finally, a qualitative comparison is made between the efficiency of the most commonly used technology measures against substrate crosstalk.

Study of substrate noise and techniques for minimization

The effects of substrate noise on analog circuits in a mixed-signal chip are described and analyzed based on measured results. Experimental data from a 0.25-/spl mu/m CMOS test chip reveals that substrate noise generated by digital circuits couples into analog circuits through circuit asymmetries and device nonlinearity, degrading analog circuit performance. In particular, a delta-sigma modulator shows over 20-dB reduction of signal-to-noise-plus-distortion ratio (SNDR) in the presence of large toggling digital inverters. To combat the effects of substrate noise, the technique of active substrate noise shaping is investigated. An implementation of active substrate noise shaping on the same test chip demonstrates over 10-dB improvement in SNDR in the 0-20-kHz band of the delta-sigma modulator in the presence of toggling digital inverters emulating I/O drivers. This technique complements existing substrate noise reduction techniques for integrated circuits without a significant penalty in power and does not require modification of analog nor digital circuits.

Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

This paper describes substrate noise reduction techniques for synchronous CMOS circuits. Low-noise digital design techniques have been implemented and measured on a mixed-signal chip, fabricated in a 0.35 /spl mu/m CMOS process on an EPI-type substrate with 10 /spl Omega/cm EPI resistivity and 4 /spl mu/m EPI layer thickness. The test chip contains one reference design and two digital low-noise designs with the same basic architecture. Measurements show more than a factor of 2 on average in r.m.s. noise reduction with penalties of 3% in area and 4% in power for the low-noise design employing a supply-current waveform-shaping technique based on a clock tree with latencies. The second low-noise design employing separate substrate bias for both n- and p-wells, dual-supply, and on-chip decoupling achieves more than a factor of 2 reduction in r.m.s. noise, with, however, a 70% increase in area, but with a 5% decrease in power consumption.

Characterization and modeling of on-chip spiral inductors for Si RFICs

The paper presents a complete characterization of on-chip inductors fabricated in BiCMOS technology. First, a study of the scaling effect of inductance on geometry and structure parameters is presented to provide a clear guideline on inductor scaling with suitable quality factors. The substrate noise analysis and noise reduction techniques are then investigated. It is shown that floating well can improve both quality factor and noise elimination by itself under 3 GHz and together with a guard ring above 3 GHz. Finally, for accurate circuit simulations, a new inductor model is developed for predicting the skin effect and eddy effect and associated quality factor and inductance.

Physical design guides for substrate noise reduction in CMOS digital circuits

Substrate noise injection in large-scale CMOS logic integrated circuits is quantitatively evaluated by 100-/spl mu/V 100-ps resolution substrate noise measurements of controlled substrate noises by a transition-controllable noise source and practical substrate noises under CMOS logic operations. The noise injection is dominated by leaks of supply/return bounce into the substrate, and the noise intensity is determined by logic transition activity, according to experimental observations. A time-series divided parasitic capacitance model is derived as an efficient estimator of the supply current for simulating the substrate noise injection and can reproduce the measured substrate noise waveforms. The efficacy of physical noise reduction techniques at the layout and circuit levels is quantified and limitations are discussed in conjunction with the noise injection mechanisms. The reduced supply bounce CMOS circuit is proposed as a universal noise reduction technique, and more than 90% noise reduction to conventional CMOS is demonstrated.