Sub-resolution Assist Feature Insertion Research Articles

CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation

In lithography process, Sub-Resolution Assist Features (SRAFs), as an essential resolution enhancement technique (RET), is applied to improve the pattern fidelity and enlarge the process window. In this paper, we propose a robust constraint-aware SRAF generation method based on continuous transmission mask (CTM). The intensity distribution on the continuous transmission mask is extracted to guide the SRAF generation. The SRAF insertion also honors the design rules, which is formulated as integer programming with quadratic constraints and solved by a fast yet efficient algorithm. A fast probe-based SRAF evolution method is proposed to determine the shapes of SRAFs. The effectiveness and efficiency are demonstrated based on the experimental results.

Sub-resolution assist feature placement with generative adversarial network

Background: As the design layout of integrated circuits (ICs) is continually scaling down, sub-resolution assist features (SRAF) have been extensively used in resolution enhancement technique applications to enhance lithography printing fidelity and widen the manufacturing process window (PW). With conventional SRAF insertion techniques, rule-based SRAF (RB-SRAF) and model-based SRAF (MB-SRAF) methods have since been widely adopted. Aim: The typical RB-SRAF is an efficient method to generate SRAFs consistently for simple designs but cannot be optimized for multiple critical patterns or complex layout schemes. Although MB-SRAF is able to achieve better PW as well as reducing conflicts between placement rules and clean-up rules, many iterations for convergence and extremely high computational costs are required. The explosion of machine learning techniques could facilitate the complex processes of mask optimization, such as SRAF insertion. Approach: Generative adversarial network was studied on a Via layer of advanced 3D NAND flash memory, by training target images and Inverse Lithography Technology (ILT) images of target patterns. GAN models, pix2pix, and CycleGAN, were first trained and then utilized to synthesize realistic ILT images. Results: These ILT images were eventually translated to polygons of SRAF with simplification process and mask manufacturing rules check constraints. The simulation results demonstrate that CycleGAN approach can place SRAF with comparable performance to mask optimization (MO) result which was optimized by the Tachyon source-mask optimizer (SMO). Conclusions: Methodologies of SRAF placement based on GANs were demonstrated in this paper. While traditional MO approach showed the best lithography performance, CycleGAN in particular was close behind and had much better performance than conventional RB-SRAF approach, whilst achieving good stability for different layout environments. Most importantly, the efficiency of SRAF insertion can be enhanced significantly through GANs.

GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks

As the integrated circuits (ICs) technology continues to scale, resolution enhancement techniques (RETs) are mandatory to obtain high manufacturing quality and yield. Among various RETs, subresolution assist feature (SRAF) generation is a key technique to improve the target pattern quality and lithographic process window. While model-based SRAF insertion techniques have demonstrated high accuracy, they usually suffer from high computational cost. Therefore, more efficient techniques that can achieve high accuracy while reducing runtime are in strong demand. In this article, we leverage the recent advancement in machine learning for image generation to tackle the SRAF insertion problem. In particular, we propose a new SRAF insertion framework, GAN-SRAF, which uses generative adversarial networks (GANs) to generate SRAFs directly for any given layout. Our proposed approach incorporates a novel layout to image encoding using multichannel heatmaps to preserve the layout information and facilitate layout reconstruction. Our experimental results demonstrate ${\sim }14.6\times $ reduction in runtime when compared to the previous best machine learning approach for SRAF generation, and ${\sim }144\times $ reduction compared to the model-based approach, while achieving comparable quality of results.

SRAF Insertion via Supervised Dictionary Learning

In modern VLSI design flow, subresolution assist feature (SRAF) insertion is one of the resolution enhancement techniques (RETs) to improve chip manufacturing yield. With aggressive feature size continuously scaling down, layout feature learning becomes extremely critical. In this article, for the first time, we enhance conventional manual feature construction, by proposing a supervised online dictionary learning algorithm for simultaneous feature extraction and dimensionality reduction. By taking advantage of label information, the proposed dictionary learning framework can discriminatively and accurately represent the input data. We further consider SRAF design rules in a global view, and design two integer linear programming models in the post-processing stage of SRAF insertion framework. The experimental results demonstrate that, compared with a state-of-the-art SRAF insertion tool, our framework not only boosts the performance of the machine learning model but also improves the mask optimization quality in terms of edge placement error (EPE) and process variation (PV) band area.

Subresolution assist features impact and implementation in extreme ultraviolet lithography for next-generation beyond 7-nm node

The next-generation beyond 7-nm node potentially requires the implementation of subresolution assist features (SRAF) with extreme ultraviolet (EUV) lithography. This paper aims at providing a clear SRAF strategy for the next-generation beyond 7-nm node designs through a series of experiments. Various factors are considered, including stochastic effects, three-dimensional (3-D) mask effects, through-slit effects, aberrations, and pixelated source mask optimization (SMO) sources. We consider process variability bands with a variety of process conditions, including focus/dose/mask bias changes and also the normalized image log-slope/image log-slope as our objective functions, to determine what the best SRAF solution is for a set of test patterns. Inverse lithography technology is implemented to optimize both the main feature (MF) mask and SRAF placement, in particular, asymmetric SRAF placement to balance the 3-D mask effects. SRAF can potentially mitigate image shift through-focus, i.e., nontelecentricity, caused by EUV 3-D shadowing effect. This shadowing effect is pattern-dependent and contributes to the overlay variation. As we approach the next-generation beyond 7-nm node, this image shift can be more significant relative to the overlay budget, hence, we further investigate the impact of SRAF placement to the image shift. Moreover, the center of focus shift due to the large 3-D mask absorber thickness can be potentially mitigated by SRAF implementation. The common process window is significantly impacted by both the center of focus shift and the individual depth of focus and is evaluated using both metal and contact layer test cases. We study the source impact to SRAF insertion by experimenting with both a symmetric source (standard source) and an asymmetric source (SMO source). Finally, we understand the importance of using full flare map and full through-slit model (including aberration variation through-slit) in the MF correction. Furthermore, we evaluate the need of using full models in SRAF insertion. This is a necessary step to determine the strategy of SRAF implementation for the next-generation beyond 7-nm node.

A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling

With the continuous shrinkage of advanced technology nodes into the sub-16-nm regime, optical proximity correction (OPC) is still the main stream to preserve acceptable wafer image quality under lithographic process variations in the foreseeable future. However, OPC is getting more aggressive to keep pace with advanced technology nodes. This results in complex mask solutions and long computation time. In this paper, we propose a novel-intensity-based OPC algorithm to find mask solutions with minimal edge placement error and process variability band area within a short computation time. This is achieved through exploiting a fast novel intensity estimation model with acceptable estimation accuracy to guide the OPC response including two-fragment shifting, corner hammering, and subresolution assist feature insertion for better convergence. Moreover, our algorithm is extended to satisfy the mask notch rule and reduce shot count for a lower mask manufacturing cost. The experimental results show that our algorithm outperforms recently published algorithms on the public benchmarks.

Detailed Placement for Enhanced Control of Resist and Etch CDs

Subresolution assist feature (SRAF) and etch-dummy-insertion techniques have been absolutely essential for process-window enhancement and CD control in photo and etch processes. However, as focus levels change during lithography manufacturing, CDs at a given ldquolegalrdquo pitch can fail to achieve manufacturing tolerances. Placed standard-cell layouts may not have the ideal whitespace distribution to allow for an optimal assist-feature insertion. This paper first describes a novel dynamic-programming-based technique for Assist-Feature Correctness (AFCorr) in detailed placement of standard-cell designs. At the same time, etch-dummy features are used in the mask data preparation flow to reduce CD skew between resist and etch processes and to improve the printability of layouts. However, etch-dummy rules conflict with the SRAF insertion because each of the two techniques requires specific design rules. We further present a novel SRAF-aware etch-dummy-insertion method (SAEDM) which optimizes the etch-dummy insertion to make the layout more conducive to the assist-feature insertion after the etch-dummy features have been inserted. Since placement of cells can create forbidden-pitch violations of resist process and can increase etch skew, the placer must also generate etch-dummy-correct placement. This can be solved by Etch-dummy Correctness (EtchCorr), which is an intelligent whitespace management for etch-dummy-corrected placement, an extension of the AFCorr methodology. These methods for enhanced resist and etch CD controls are validated on industrial test cases with respect to wafer printability, database complexity, and device performance. For benchmark designs, we validate the four methodologies: 1) AFCorr; 2) SAEDM; 3) AFCorr SAEDM; and 4) AFCorr EtchCorr SAEDM. The AFCorr placement perturbation achieves a significant reduction in forbidden pitches between polysilicon shapes. Using 1) flow, forbidden-pitch count of photo process is reduced by 76%-100% for 130 nm and by 87%-100% for 90 nm. Our novel Corr design-perturbation technique, which combines the AFCorr and EtchCorr methods, facilitates additional SRAF and etch-dummy insertions and, thus, reduces the CD skew between the photo and etch processes. After Corr with SAEDM, edge-placement-error count is also reduced by 91%-100% in the resist CD and by 72%-98% in the etch CD. Our methods provide a substantial improvement in CD control with negligible timing, area, and CPU overhead. The advantages of such correctness methods are expected to increase in future technology nodes.