Submicron CMOS Devices Research Articles

An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique

Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

Enhanced I ON/I OFF in ultra deep submicron CMOS devices using grooved nMOSFETs in comparison to planar nMOSFET

To manage the increasing static leakage in low power applications and reducing ON‐OFF current ratio due to scaling limitations, solutions for leakage reduction as well as improving the current drive of the device are sought at the device design and process technology levels. At the device design level, the important low power variables are the threshold voltage, the gate leakage current, the subthreshold leakage current and the device size. Grooved‐gate MOS devices are considered as the most promising candidates for use in submicron and deep submicron regions as they can overcome the short‐channel effects effectively. By varying the corner angle and adjusting other structural parameters such as junction depth, channel doping concentration, negative junction depth and oxide thickness, leakage current in nMOS devices can be minimised. In this article, 90, 80, 70, 60 and 50 nm devices are simulated using Devedit and Deckbuild module of Silvaco device simulator. The simulated results show that by changing the structural parameters, ON‐OFF current ratio is improved and maintained constant even in the deep submicron region. This study can be helpful for low power applications as the static leakage is drastically reduced, as well as applicable to high speed devices as the ON current is maintained at a constant value. The results are compared with those of corresponding conventional planar devices to bring out the achievements of this study.

Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications

In recent years, the demand for power sensitive designs has grown significantly due to the fast growth of battery-operated portable applications. As the technology scaling continues unabated, subthreshold device design has gained a lot of attention due to the low-power and ultra-low-power consumption in various applications. Design of low-power high-performance submicron and deep submicron CMOS devices and circuits is a big challenge. Short-channel effect is a major challenge for scaling the gate length down and below 0.1 μm. Detailed review and potential solutions for prolonging CMOS as the leading information technology proposed by various researchers in the past two decades are presented in this paper. This paper attempts to categorize the challenges and solutions for low-power and low-voltage application and thus provides a roadmap for device designers working in the submicron and deep submicron region of CMOS devices separately.

STI Post CMP Cleaning Solution Development

Shallow Trench Isolation (STI) is the standard isolation method for fabrication of submicron CMOS devices. Ceria based slurries are often used for the chemical mechanical planarization (CMP) of STI structures. It is essential therefore, to clean the structure after the CMP process to remove the ceria and other organic residues, usually resulting from the slurry. In this paper, post CMP cleaning of STI wafers with a specially formulated clean solution has been discussed.

Effect of the pre-gate oxide cleaning temperature on the reliability of GOI and devices performances in deep submicron CMOS technology

This paper reports the impacts of the pre-gate oxide cleaning on the statistic fluctuations of a deep submicron CMOS devices’ saturation current, leakage current, threshold voltage, and gate oxide integrity (GOI) in detail. These statistic distributions are based on a foundry’s batch production line. This study concludes that the pre-gate oxide hot water clean enhances silicon surface’s micro-roughness and stress effects, thus are responsible to the higher fluctuations of devices performance distributions. Similar results were found in the GOI of the thin gate oxide. The micro-roughness and stress effects of silicon surface were evaluated systematically through atom force microscope (AFM) and thin film stress measurement system, and their mechanisms are interpreted comprehensively with schematic models.

Process-induced mechanical stress effects on deep submicron CMOS device

With the continuous downscaling of CMOS technology, process-induced mechanical stress effects become remarkable with the shrinkage of active region. Many processing steps individually or collectively contribute to mechanical stress development. The stress results in not only the layout dependency of device performances, but also diverse reliability issues, which would shorten the chip lifetime. In many cases, stress-related problems are determinative of IC yield. Here, based on the summary of mechanical stress sources, we review the achievements to date in observing and understanding these stress problems, and propose the prospective considerations when analyzing stress-related phenomenon.

Effect of STI-induced mechanical stress on leakage current in deep submicron CMOS devices

The shallow trench isolation (STI) induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper, we designed two types of devices to investigate this effect, and all leakage components, including sub-threshold leakage (Isub), gate-induced-drain-leakage (IGIDL), gate edge-direct-tunnelling leakage (IEDT) and band-to-band-tunnelling leakage (IBTBT) were analysed. For NMOS, Isub can be reduced due to the mechanical stress induced higher boron concentration in well region. However, the GIDL component increases simultaneously as a result of the high well concentration induced drain-to-well depletion layer narrowing as well as the shrinkage of the energy gap. For PMOS, the only mechanical stress effect on leakage current is the energy gap narrowing induced GIDL increase.

Structural and surface properties of Si 1− xGe x thin films obtained by reduced pressure CVD

This paper investigates the structure and surface characteristics, and electrical properties of the polycrystalline silicon-germanium (poly-Si 1− x Ge x ) alloy thin films, deposited by vertical reduced pressure CVD (RPCVD) in the temperature range between 500 and 750 °C and a total pressure of 5 or 10 Torr. The samples exhibited a very uniform good quality films formation, with smooth surface with rms roughness as low as 7 nm for all temperature range, Ge mole fraction up to 32% (at 600 °C), textures of 〈2 2 0〉 preferred orientation at lower temperatures and strong 〈1 1 1〉 at 750 °C, for both 5 and 10 Torr deposition pressures. The 31P + and 11B + doped poly-Si 1− x Ge x films exhibited always lower electrical resistivity values in comparison to similar poly-Si films, regardless of the employed anneal temperature or implantat dose. The results indicated also that poly-Si 1− x Ge x films require much lower temperature and ion implant dose than poly-Si to achieve the same film resistivity. These characteristics indicate a high quality of obtained poly-Si 1− x Ge x films, suitable as a gate electrode material for submicron CMOS devices.

Total-ionizing-dose effects on isolation oxides in modern CMOS technologies

This paper presents experimental data on the total dose response of deep sub-micron bulk CMOS devices and integrated circuits. Ionizing radiation experiments on shallow trench isolation (STI) field oxide MOS capacitors (FOXCAP) indicate a characteristic build-up of radiation-induced defects in the dielectric. In this paper, capacitors fabricated with STI, thermal, SIMOX and bipolar base oxides of similar thickness are compared and show the STI oxide to be most susceptible to radiation effects. Experimental data on irradiated shift registers and n-channel MOSFETs are also presented. These data indicate that radiation damage to the STI can increase the off-state current of n-channel devices and the standby current of CMOS integrated circuits.

Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use

Analog-to-Digital converters (ADCs) for video applications have made exciting progress in miniaturization and power reduction in the past 20 years. This paper mainly describes the key technologies for miniaturization and power reduction of 10-bit video-frequency ADCs. By reviewing useful architectures and circuit schemes for video-frequency ADCs, self-calibration techniques and interleaving techniques are surveyed. The subranging pipeline look-ahead ADC architecture is introduced. It has a potential for reducing power consumption and improving conversion rate when minute deep submicron CMOS devices are used with low supply voltage.

Chapters report

In the past four months, the SSCS Denver Chapter hosted meetings spanning technology, device, reliability, and design topics. In December 2004, newly elected chapter chair Dr. Alvin Loke of Agilent Technologies presented a tutorial on deep submicron CMOS device technology and its impact on circuit design. Dr. Loke summarized the importance of understanding the impact of effects such as halo implants, active area mechanical stress, and well implant mask proximity as well as limitations in IC manufacturing to successfully design analog circuits in deep submicron CMOS.

The impact of etch-stop layer for borderless contacts on deep submicron CMOS device performance—a comparative study

The impact of etch-stop layers (ESLs) of borderless contact (BLC) on transistor characteristics, especially for NMOSFETs, was studied concerning on the ESL-induced mechanical stress. Two new ESL schemes using dual etch-stop layers: (scheme A) SiON (bottom)/SiN (top) and (scheme B) SiN (bottom)/SiON (top) were studied and implemented into device fabrication. The electrical performance of the N- and PMOSFETs was characterized. It has been found that by using scheme A, a 2.7% improvement of I on versus I off margin as compared with the single-layer process is achieved on NMOSFETs. The scheme A results in a loss of the PMOS margin by 1.4%, which is still within the specifications. However, scheme B, which uses a SiN as the bottom layer, presents a slightly less improvement of process margin (1.7%) on NMOSFETs with much larger loss of process margin (2.3%) on PMOSFETs. Our results suggest that optimization of ESL for borderless contact could play an important role in determining transistor performance for deep submicron CMOS.

Rail-to-rail constant- gm operational amplifier for video applications

This paper presents an operational amplifier (op-amp) with input/output rail-to-rail capability suitable for video applications. The input stage, which is based on two complementary differential pairs, provides a constant transconductance over the entire input common-mode voltage range, whereas a class-AB output stage with an accurate control of the quiescent current ensures rail-to-rail output swing even in the presence of a heavy load. Both the input stage transconductance and the output stage quiescent current are controlled by means of static loops, which allows high-frequency operation of the amplifier. In addition, the proposed constant-transconductance technique does not depend on the I– V characteristics of the input transistors—it is therefore compatible with modern submicron CMOS devices—and does not rely on any accurate matching between the complementary input pairs. The op-amp was designed to operate with 3 V of supply voltage and fabricated in 0.8-μm CMOS technology. The measured open-loop gain and unity gain-bandwidth for a 100-Ω∥100-pF load are 60 dB and 32 MHz, respectively, while the output swing with the same output load reaches 83% of the total supply voltage.

High- k dielectrics by UV photo-assisted chemical vapour deposition

An overview of our recent work on thin films of metal oxides deposited on silicon by a novel excimer lamp-assisted ultraviolet injection liquid source CVD (UVILS-CVD) process for advanced high- k gate dielectrics applications will be presented. Recent results on TiO 2, Ta 2O 5, ZrO 2, HfO 2, and TiO 2-doped Ta 2O 5 will be demonstrated. The physical, structural, surface and interfacial properties and electrical characterisation of the as-deposited and UV-annealed new high dielectric constant (high- k) materials, determined using ellipsometry, Fourier transform infrared spectroscopy, X-ray photoelectron spectroscopy, UV spectrophotometry, SEM, TEM and C– V, I– V measurements, showed that good quality layers could be produced. The investigation of high- k dielectrics grown by the UVILS-CVD process clearly demonstrates that low cost, high power density excimer lamp systems can provide an interesting alternative to conventional UV lamps and excimer lasers for industrial large-scale low temperature materials processing. UVILS-CVD is a promising technique for the controlled deposition of ultra-thin high- k metal-oxide dielectrics for deep sub-micron CMOS devices at temperatures as low as 350 °C.

Obtaining silicide free spacers by optimizing sputter etch for deep submicron CMOS processes

In this paper, we have shown that the sputter etch before cobalt deposition during the silicide processing of a deep submicron CMOS device fabrication needs to be optimized in order to eliminate a detrimental origin of gate (G) to source (S)/drain (D) bridging. It is known that Co cannot reduce even a thin layer of native oxide. Therefore, it is necessary to ensure that Co is deposited on a very clean Si surface. To ensure this, an in-situ sputter etch is commonly conducted before Co deposition. It is observed that this sputter etch process can sputter Si from the S/D area and deposit them on the sidewall spacer (SWS). This sputtered Si in turn will react with deposited Co and form silicide. The worst case leakage currents from poly-Si to composite for long (10 m) and narrow (0.18 micron) poly lines are shown to be on the order of milliampere. Transmission electron microscope (TEM) micrographs included show the existence of cobalt silicide layers (/spl sim/8 nm thick) over sidewall spacer. The silicide thickness on the sidewall spacer is correlated with resistance value calculated from current and voltage (I-V) measurements. The need for optimizing the sputter etch recipe has been validated by TEM and I-V measurements.

The effect of doping methods on electrical properties and micromorphology of polysilicon gate electrode in submicron CMOS devices

The effect of doping methods on electrical properties and micromorphology of polysilicon gate electrode in submicron CMOS devices

Mapping of electrostatic potential in deep submicron CMOS devices by electron holography.

Quantitative two-dimensional maps of electrostatic potential in device structures are obtained using off-axis electron holography with a spatial resolution of 6 nm and a sensitivity of 0.17 V. Estimates of junction depth and variation in electrostatic potential obtained by electron holography, process simulation, and secondary ion mass spectroscopy show close agreement. Measurement artifacts due to sample charging and surface "dead layers" do not need to be considered provided that proper care is taken with sample preparation. The results demonstrate that electron holography could become an effective method for quantitative 2D analysis of dopant diffusion in deep-submicron devices.

Thermal stability of ultra-shallow junctions in silicon formed by molecular-beam epitaxy using boron delta doping

Ultra-shallow junction layers are required for deep submicron CMOS and quantum devices. Low-temperature (320 °C) molecular-beam epitaxy was used to form highly conductive, ultra-shallow layers in silicon using boron delta doping. The as-grown junction depths, determined with secondary ion mass spectrometry, ranged from 7 to 18 nm. A minimum resistivity of 3×10 −4 Ω-cm was obtained when the delta-doped layers were spaced 2.5 nm apart. The sheet resistances of the epitaxial layers, plotted as a function of junction depth, followed the theoretical curve for a box-doped layer having a boron doping concentration equal to the solid solubility limit, 6×10 20 cm −3. Minimal change was detected in either the atomic profiles or the resistivity after a 10 s rapid thermal anneal (RTA) or a 10 min furnace anneal (FA) up to 700 °C. The sheet resistance of the as-grown shallow junction are substantially less than that obtained by ion implantation. Only after the 800 °C FA did the MBE-grown layers degrade to have as large a sheet resistance as the best ion implanted layers.

Strain Field Distribution in Submicron Devices by TEM/CBED. A European Project

Abstract It is now widely accepted that one of the major issues for the future deep sub-micron integrated circuit (IC) technologies regarding yield, device performance and stability and device and product reliability, is the mechanical stress built up in the layers and substrate. It is therefore important to give a quantitative account of these stresses and this can only be achieved by disposing of reliable, performant (as to spatial resolution) and quantitative techniques for the local stress determination in the substrate, of adequate and dedicated process simulation tools and of sensitive methods to analyse the stress effects on device performance. The only experimental technique presently available which allows the strain field distribution in sub-micron CMOS devices is the convergent beam electron diffraction technique of the transmission electron microscopy. Its sensitivity is of the order of 10-4 and its spatial resolution is of 1 nm if a TEM/FEG is employed.

Cryogenic temperature non-scaling of linear resistance in n-MOSFETs exhibiting reverse short-channel effect

An enhancement of the non-scaling of the linear resistance with channel length is observed at low temperatures, despite reduced reverse short channel effect. This imposes a significant limitation on the low temperature operation of deep submicron CMOS devices. An increased surface roughness scattering in shorter channel devices is suggested to explain the gate overdrive and temperature dependence.