SubBytes Operation Research Articles

Enhanced AES-256 cipher round algorithm for IoT applications

Objectives: Networks have become a significant mode of communication in recent years. As a result, internet security has become a critical requirement for secure information exchange. Cryptography is used to securely send passwords over large networks. Cryptographic algorithms are sequences of processes used to encipher and decipher messages in a cryptographic system. One of those is the Advanced Encryption Standard (AES), which is a standard for data encryption in hardware and software to hide sensitive and vital information. The main objective is to design an AES system with modifications by the addition of primitive operations which can withstand several attacks and is more efficient.Method: AES works with three different key lengths: 128-bit keys, 192- bit keys, and 256-bit keys. The early rounds of AES have a poor diffusion rate. Better diffusion properties can be brought about by putting in additional operations in the cipher round and key generation algorithm of the conventional AES.Findings: The diffusion characteristics of the conventional AES and the proposed methodology are compared using the avalanche effect. The proposed AES algorithm shows an increased avalanche effect, which proves it to be more secure than the conventional AES. The proposed algorithm is executed on Vivado 2016.2 ISE Design Suite and the results are targeted on Zybo–Zynq Z-7010 AP SoC development board.Novelty: In addition, this paper also proposes an improved AES algorithm that was accomplished by altering the sub-bytes operation. This change was made to make it more reliant on round keys. This algorithm was also extended to a higher key length of 256 bits which makes the algorithm less vulnerable to attacks.

Bitsliced Implementation of Non-Algebraic 8×8 Cryptographic S-Boxes Using ×86-64 Processor SIMD Instructions

The article is devoted to software bitsliced implementation of randomly generated <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times 8$ </tex-math></inline-formula> S-Box block ciphers, focused on the use of logical SIMD instructions from the SSE, AVX and AVX-512 extensions in ×86-64 processors. A heuristic algorithm for minimizing non-algebraic S-Boxes in three logical bases is proposed: universal—based on logical instructions AND, OR, XOR, NOT, which allows implementation on any 8/16/32/ 64-bit processors; extended—based on the instructions AND, OR, XOR, NOT, AND-NOT, which allows implementation on ×86-64 processors; ternary—based on ternary logic instructions, for implementation on ×86-64 processors with AVX-512 support. On average, bitsliced representations of non-algebraic S-Boxes in these logical bases require 400/380/200 logical instructions, respectively. The performance of bitsliced implementations of the S-Box cipher “Kalyna” using logical instructions SSE/AVX/ AVX-512 for the Intel Xeon Skylake-SP processor was measured. A fast alternative—non-bitsliced approach to the bytesliced SubBytes operation based on the AVX-512VBMI extension, resistant to timing and cache attacks—is proposed.

Side-Channel Attacks on Masked Bitsliced Implementations of AES

In this paper, we provide a detailed analysis of CPA and Template Attacks on masked implementations of bitsliced AES, targeting a 32-bit platform through the ChipWhisperer side-channel acquisition tool. Our results show that Template Attacks can recover the full AES key successfully within 300 attack traces even on the masked implementation when using a first-order attack (no pre-processing). Furthermore, we confirm that the SubBytes operation is overall a better target for Template Attacks due to its non-linearity, even in the case of bitsliced implementations, where we can only use two bits per key byte target. However, we also show that targeting the AddRoundKey can be used to attack bitsliced implementations and that, in some cases, it can be more efficient than the SubBytes attack.

ПРОГРАМНА BITSLICED-ІМПЛЕМЕНТАЦІЯ ШИФРУ «КАЛИНА» ОРІЄНТОВАНА НА ВИКОРИСТАННЯ SIMD-ІНСТРУКЦІЙ МІКРОПРОЦЕСОРІВ З АРХІТЕКТУРОЮ Х86-64

The article is devoted to software bitsliced implementation of the Kalyna cipher using vector instructions SSE, AVX, AVX-512 for x86-64 processors. The advantages and disadvantages of different approaches to efficient and secure block cipher software implementation are shown. It is noted that bitslicing technology combines high speed and resistance to time and cache attacks, but its application to the Kalyna cipher is not available at the moment. The basic approaches to data representation and bitsliced encryption operations are considered, special attention is paid to the effective implementation of SubBytes operation, which largely determines the final performance. Existing methods for minimizing logical functions have been shown to either fail to produce the result in bitsliced format in the case of 8-bit non-algebraic SBoxs, or far from optimal. A heuristic algorithm for minimizing logic functions describing Kalyna SBoxes using the operations of AND, OR, XOR, NOT available in the instruction set of low- and high-end processors is proposed. The results show that a bitsliced description of one SBox requires about 520 gates, which is significantly less than other methods. Possible ways to increase performance by regrouping data into bitsliced variables before and after the SubBytes operation are indicated, which results in more efficient use of vector registers. The bitsliced implementations of Kalyna cipher were measured using C++ compilers from Microsoft and GCC for the Intel Xeon Skylake-SP processor. The results of the bitsliced Kalyna implementation can also be transferred to processors that do not support SIMD instructions, including low-end, to increase resistance to attacks through third-party channels. They also enable switching to ASIC or FPGA-based bitsliced implementation of Kalyna.

A Hybrid Countermeasure-Based Fault-Resistant AES Implementation

A Fault-Resistant scheme has been proposed to secure the Advanced Encryption Standard (AES) against Differential Fault Analysis (DFA) attack. In this paper, a hybrid countermeasure has been presented in order to protect a 32-bits AES architecture proposed for resource-constrained embedded systems. A comparative study between the most well-known fault detection schemes in terms of fault detection capabilities and implementation cost has been proposed. Based on this study, we propose a hybrid fault resistant scheme to secure the AES using the parity detection for linear operations and the time redundancy for SubBytes operation. The proposed scheme is implemented on the Virtex-5 Xilinx FPGA board in order to evaluate the efficiency of the proposed fault-resistant scheme in terms of area, time costs and fault coverage (FC). Experimental results prove that the countermeasure achieves a FC with about 98,82% of the injected faults detected during the 32-bits AES process. The area overhead of the proposed countermeasure is about 14% and the additional time delay is about 13%.

Using linear codes as a fault countermeasure for nonlinear operations: application to AES and formal verification

Recently, Bringer et al. [10] introduced a new countermeasure based on linear codes. This elegant design aims at protecting advanced encryption standard against both side-channel attacks and fault attacks (FA). However, the fault detection during nonlinear operations (for example SubBytes operation) was left as an open question. The present work studies how linear systematic error correcting codes can simply be used to detect fault injections during nonlinear operations in a symmetric block cipher. In particular, for the faults that cause errors with limited Hamming weight, this method can lead to interesting detection capabilities. Considering this way of protecting AES encryption against FA, a concrete implementation is presented. For a given fault model, a methodology of formal verification is applied to some parts of this implementation, assessing the fault resistance of one linear operation AddRoundKey and one nonlinear operation SubBytes.

Variety of Scalable Shuffling Countermeasures against Side Channel Attacks

IoT devices have very strong requirements on all the resources such as memory, randomness, energy and execution time. This paper proposes a number of scalable shuffling techniques as countermeasures against side channel analysis. Some extensions of an existing technique called Random Start Index (RSI) are suggested in this paper. Moreover, two new shuffling techniques Reverse Shuffle (RS) and Sweep Swap Shuffle (SSS) are described within their possible extensions. Extensions of RSI, RS and SSS might be implemented in a constrained environment with a small data and time overhead. Each of them might be implemented using different amount of randomness and thus, might be fine-tuned according to requirements and constraints of a cryptographic system such as time, memory, available number of random bits, etc. RSI, RS, SSS and their extensions are described using SubBytes operation of AES-128 block cipher as an example, but they might be used with different operations of AES as well as with other algorithms. This paper also analyses RSI, RS and SSS by comparing their properties such as number of total permutations that might be generated using a fixed number of random bits, data complexity, time overhead and evaluates their resistance against some known side-channel attacks such as correlation power analysis and template attack. Several of proposed shuffling schemes are implemented on a 8-bit microcontroller that uses them to shuffle the first and the last rounds of AES-128.&#x0D;

On-Chip Nanoscale Capacitor Decoupling Architectures for Hardware Security

This paper presents new power analysis attack (PAA) countermeasures for nanoscale cryptographic devices. Specifically, three circuit level architectures called partial decoupling architecture, full decoupling architecture, and randomized switch box architecture are developed and analyzed. The architectures' primary feature is the use of on-chip nMOS gate capacitors as intermediate power storage elements to decouple the power supply from internal low-power modules processing sensitive data. The proposed countermeasures are algorithm independent and allow different tradeoffs between security protection and the incurred overheads. Test benches of the proposed architectures were simulated in 65-nm TSMC CMOS technology. A correlation PAA was performed for each test bench targeting a custom implementation of the advanced encryption standard subbytes operation. All architectures were found to resist the correlation PAA at the power supply, with the more complex architectures also offering protection against invasive attacks. The success value indicator was used to analyze the effectiveness of the countermeasures. It was found that all architectures provided a negative value at the power supply, showing protection against PAAs. We demonstrate that the use of nMOS gate capacitors can help to increase security and present a feasibility analysis focused on the needed decoupling capacitances.

AES side-channel countermeasure using random tower field constructions

Masking schemes to secure AES implementations against side-channel attacks is a topic of ongoing research. The most sensitive part of the AES is the non-linear SubBytes operation, in particular, the inversion in GF(28), the Galois field of 28 elements. In hardware implementations, it is well known that the use of the tower of extensions \({GF(2)\subset GF(2^2)\subset GF(2^4)\subset GF(2^8)}\) leads to a more efficient inversion. We propose to use a random isomorphism instead of a fixed one. Then, we study the effect of this randomization in terms of security and efficiency. Considering the field extension GF(28)/GF(24), the inverse operation leads to computation of its norm in GF(24). Hence, in order to thwart side-channel attack, we manage to spread the values of norms over GF(24). Combined with a technique of boolean masking in tower fields, our countermeasure strengthens resistance against first-order differential side-channel attacks.

Pipelined AES on FPGA with support for feedback modes (in a multi-channel environment)

Two designs have been presented for high throughput pipelined implementation using field-programmable gate arrays (FPGAs) of the advanced encryption standard (AES). Both are believed to be faster than the existing FPGA designs and achieve throughputs of 30 and 28 Gbps. The fastest design achieves a throughput, for either encipher or decipher, in excess of 30 Gbps using a Xilinx Spartan-III part and allows key changes every 120 cycles. A second design achieves a throughput of 28 Gbps using a Xilinx Virtex-II part and supports both key and encipher/decipher changes every clock cycle. In order to achieve this, careful floor planning and a novel pipelined key expander were developed together with modifications to the MixColumns and composite field implementation of the SubBytes operation. Such an architecture has application for servers supporting multiple AES secure channels and can support, in a multi-channel environment, any feedback mode, including cipher block chaining. Previous pipelined designs have not shown this capability