Sub-threshold Standard Cell Library Research Articles

65 nm sub‐threshold logic standard cell library using quasi‐Schmitt‐trigger design scheme and inverse narrow width effect aware sizing

In this study, the authors propose a sub-threshold standard cell library in which the quintessence is a quasi-Schmitt-trigger logic design scheme and the inverse narrow width effect aware sizing method. The techniques can improve the I on-to-I off ratio of the logic cells effectively and provide a significant suppression in leakage current, enhancing the robustness of the circuits. Simulation results show that the NAND3 and NOR3 logics with the new techniques achieve 40–60% and 30–50% reductions in leakage power compared with conventional logic circuits, respectively, when the voltage is scaled down to sub-threshold region. Again, they also exhibit considerable improvements in process variation immunity and power-delay product.

An optimal device sizing for a performance-driven and area-efficient subthreshold cell library for IoT applications

Ultra-low power design techniques specifically subthreshold designs, play a vital role in Internet of things systems that survive on limited power budget or harvested energy sources. In this paper, the width and length of a transistor operating at subthreshold region are optimized considering the nano-scale effects such as reverse short channel effect and inverse narrow width effect, which improves performance, reduces area, minimizes sensitivity to process variation and reduces energy consumption. A subthreshold standard cell library consisting of 45 standard cells is designed. The physical synthesis of ISCAS′85 benchmark circuits and a floating point unit shows that energy savings in area-mapped design are up to 23% whereas area savings in performance-mapped design are up to 30%. The measurement results from a test chip fabricated in industrial 130 nm technology demonstrate a performance improvement of up to 27%, reduction in delay variability of up to 24% and energy savings of 18%.

A light-powered sub-threshold microprocessor

This paper presents an 8-bit sub-threshold microprocessor which can be powered by an integrated photosensitive diode. With a custom designed sub-threshold standard cell library and 1 kbit sub-threshold SRAM design, the leakage power of 58 nW, dynamic power of 385 nW @ 165 kHz, EDP 13 pJ/inst and the operating voltage of 350 mV are achieved. Under a light of about 150 kLux, the microprocessor can run at a rate of up to 500 kHz. The microprocessor can be used for wireless-sensor-network nodes.