Sub-harmonic Down-conversion Research Articles

A 220‐GHz CMOS passive subharmonic downconverter for low‐IF applications

This paper presents a 220-GHz subharmonic downconverter with high conversion gain (CG) and low noise figure (NF) implemented in 28 nm bulk CMOS, including a core mixer and an intermediate frequency (IF) amplifier. Based on the traditional quasi-subharmonic mixer, new gate-shorted technology is presented to improve NF and CG by adding a source inductor to reduce the loss of radiofrequency signals. In addition, the impedance transformation network provides passive voltage gain to suppress the noise of the IF amplifier. The downconverter achieves a minimum single-sidebandNF of 15.5 dB and a maximum CG of 21.3 dB when the IF frequency is 10 MHz. The 1 dB compression point of the downconverter is −30 dBm and consumes 8 mA current with an operating voltage of 0.9 V. The core area of the chip is 200 × 160 µm2

A V-Band High Gain Sub-Harmonic Down-Conversion Mixer Using PMOS Cross Couple Pair to Implement Negative Impedance and Current-Bleeding Technique

In this brief, we present a high gain sub-harmonic mixer using PMOS cross couple pair ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CCP</i> ) to implement the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">negative impedance</i> and current-bleeding technique at 60 GHz. In order to increase conversion gain, we adopt the PMOS <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CCP</i> for the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula> -boost technique to raise the overall transconductance between <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RF</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LO</i> stages. We also use it for current bleeding to reduce the loss of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LO</i> switches. Thus, the overall conversion gain can be improved by PMOS <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CCP</i> . At IF stage, the differential signal is converted to single-ended signal by an active balun. The active balun not only can offer gain, but also can cancel out common-mode noise to improve noise figure. The measured peak gain is 6.95 dB at 61 GHz under <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LO</i> power of 1 dBm at 30 GHz. Under the different four channels at 60 GHz, the measured <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IP1dB</i> is better than −9.4 dBm. The measured 3-dB <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RF</i> bandwidth is from 57–67 GHz and 3-dB <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IF</i> bandwidth is 1.1 GHz. Total <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</i> power consumption is only 16 mW at 1 dBm <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LO</i> power for 1.2 V supplied voltage. To our best knowledge, this subharmonic mixer has the highest gain and better <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FoM</i> among active mixers at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> -band.

425-to-25-GHz CMOS-Integrated Downconverter

An integrated 425-GHz radio frequency (RF) to 25-GHz intermediate frequency (IF) second-order subharmonic downconverter, including an on-chip 8X local oscillator (LO) signal multiplier circuit that provides ~1 dBm at 200 GHz from an externally applied 25-GHz signal, and a 25-GHz IF amplifier, achieves a conversion gain of 6.7 dB and a noise figure of ~17 dB. The downconverter consumes 190 mW of dc power. Compared to the previously reported CMOS and SiGe HBT receivers/downconverters operating around 400 GHz and above, the downconverter achieves ~18-dB lower single side band noise figure. Finally, a passive switching mixer can have an available output noise spectral density less than kT, which can make its NF less than its conversion loss.

A Wideband Subharmonic Mixer Incorporating Signal Interference Technique Based Isolation Circuit

A broadband (8.7 GHz – 11.5 GHz) performing passive sub-harmonic down-conversion mixer using signal interference technique (SIT) is demonstrated, designed and reported in this paper. The local oscillator (LO) frequency is half of the radio frequency (RF) for the 2xsub-harmonic mixer architecture; therefore, for the RF lying in the range 8.7 GHz to 11.5 GHz, required LO frequency range is 4.25 GHz to 5.65 GHz with 0.2 GHz fixed intermediate frequency (IF). With a broadband operation, designed prototype shows single sideband down-conversion loss in the range 9.6 dB – 12.6 dB. Moreover, large-signal testing infers an adequate linear trait of the proposed design, showing -3 dBm and 11.32 dBm for the 1 dB compression point and third order input intercept point, respectively.

A 45- to 64-GHz ultra-low-power and low-LO-power sub-harmonic down-conversion mixer with merged self-biased trans-impedance amplifier in 90-nm CMOS

A 45- to 64-GHz ultra-low-power single-ended sub-harmonic down-conversion mixer with a merged structure fabricated in 90-nm CMOS process with triple-well NMOS devices is presented. The mixer core is merged directly with self-biased trans-impedance amplifier (TIA) to omit its traditional load stage and to enhance the conversion gain. By using weak-inversion bias technique in a source-driven topology, the mixer core only needs quiescent current of μA which can be supported from TIA via the feedback resistor. The sub-harmonic mixers can work effectively for millimeter wave (MMW) system by employing local oscillator (LO) frequency that is only half of the fundamental mixer. When operating with the optimal low LO power of −3.5 dBm at 30 GHz, the mixer exhibits a maximum conversion gain (CG) of 6.4 dB and 2 LO-to-RF isolation higher than 46.5 dB from 45 to 64 GHz. The total power consumption is 1 mW at 0.8 V. The calculated figure of merits (FOM) with the consideration of CG and power consumption is excellent among the reported mixers operating at V-band in CMOS process.

A 0.12-&lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;${\hbox{mm}}^{2} $&lt;/tex&gt;&lt;/formula&gt; 2.4-GHz CMOS Inductorless High Isolation Subharmonic Mixer With Effective Current-Reuse Transconductance

In this work, the design of an inductorless, high-isolation, and high conversion gain fully differential subharmonic down-conversion mixer for 2.4-GHz wireless application is presented. A complementary current-reuse technique is adopted between the transconductance and the local oscillator (LO) switching stage to boost the conversion gain without additional power consumption in the concept of reusing the dc current of the LO switching stage. The LO switching transistors are driven by a 25% duty cycle input to further enhance the conversion gain and improve the noise-figure performance. An active balun is integrated in the design for single-balanced to differential conversion or vice-versa, along with an RC poly phase filter to generate quadrature LO signals from a differential input signal. The subharmonic mixer is fabricated in a 0.13- $\mu{\hbox{m}}$ standard CMOS technology with a core chip dimension of 313 $\mu{\hbox{m}}\times\,$ 372 $\mu{\hbox{m}}$ and a power consumption of 5.82 mW from a supply voltage of 1.2 V. Experimental results show a conversion gain of 13.61 dB, an input-referred third-order intercept point of $-{\hbox{4.46 dBm}}$ , a noise figure of 20 dB, and an isolation greater than 50 dB between the LO, RF, and IF ports. The proposed inductorless subharmonic mixer has a competitive performance in size with high isolation performance and highest conversion gain in comparison to other published works.

InP HBT IC Technology for Terahertz Frequencies: Fundamental Oscillators Up to 0.57 THz

We report on the development of a 0.25-μm InP HBT IC technology for lower end of the THz frequency band (0.3-3 THz). Transistors demonstrate an extrapolated f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of >;800 GHz while maintaining a common-emitter breakdown voltage (BVCEO) >;4 V. The transistors have been integrated in a full IC process that includes three-levels of interconnects, and backside processing. The technology has been utilized for key circuit building blocks (amplifiers, oscillators, frequency dividers, PLL, etc), all operating at ≥300 GHz. Next, we report a series of fundamental oscillators operating up to 0.57 THz fabricated in a 0.25-μm InP HBT technology. Oscillator designs are based on a differential series-tuned topology followed by a common-base buffer, in a fixed-frequency or varactor-tuned scheme. For ≥400 GHz designs, a subharmonic down-conversion mixer is integrated to facilitate spectrum measurement. At optimum bias, the measured output power was -6.2, -5.6, and -19.2 dBm, for 310.2-, 412.9-, and 573.1-GHz designs, respectively, with P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DC</sub> ≤ 115 mW. Varactor-tuned designs demonstrated 10.6-12.3 GHz of tuning bandwidth up to 300 GHz.

A 24 GHz Subharmonic Direct Conversion Receiver in 65 nm CMOS

Scaled CMOS proves to be suitable for the design of transceiver ICs at micro- and millimeter-waves. The effort is presently toward compact and low-power solutions in view of integrating several transceivers on the same chip enabling phased array systems. In this paper we present a 24 GHz receiver, based on a subharmonic direct conversion architecture, designed in a 65 nm node. The local oscillator takes advantage of the half frequency operation proving significantly lower power consumption when compared to conventional solutions running at received frequency. Stacked switches for subharmonic down-conversion are passive to save voltage room, current driven and loaded by a transresistance amplifier. Optimum biasing of the switches allows maximizing linearity while saving power in the baseband. The integrated LNA matching network is the bottleneck toward low sensitivities. The LNA design trades-off power consumption, gain and sensitivity. Detailed insights into implementation issues, critical in a single-ended topology where both forward and return signal paths have to be supported, are provided. The chip consumes 78 mW and occupies 1.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of active area. Experiments show: 30.5 dB gain, 6.7 dB NF, -13 dBm IIP3.

Design of a KA-Band Image Rejection Sub-Harmonic Down-Converter MMIC

A Ka band image rejection sub-harmonic down-converter monolithic microwave integrated circuit (MMIC) is proposed. It contains a radio frequency (RF) amplifier, a broadband Lange coupler and two balanced mixers with two compact Marchand Baluns. The converter is fabricated by a commercial GaAs 0.2 μm pseudomorphic high electron mobility transistor (pHEMT) process, the size of which is 1.5 mm × 2 mm. Moreover, an improved nonlinear stability analysis method is presented in this paper. Based on the auxiliary generator (AG) technology, the method can analyze the nonlinear stability of circuits under the terminal impedance mismatched condition by setting the terminal load impedances as optimized variables. This method is applied to the sub-harmonic down-converter and is validated by the simulation and experiment. Experimental results show that from 30 GHz to 40 GHz, the conversion loss (CL) of the converter is less than 10 dB, and the image refection ratio (IMRR) is more than 15 dB.

Ku-band SiGe HBT I/Q subharmonic mixer with reactive quadrature generators

This article demonstrates a high-frequency 0.35-μm SiGe HBT subharmonic downconverter with reactive in-phase and quadrature-phase (I/Q) generators.Two reactive I/Q generators are integrated in our work to provide differential quadrature RF and LO signal. The I/Q subharmonic downconverter with single-ended LO, RF, and IF (I/Q) ports has a conversion gain of 1 dB, IP1dB of −10 dBm, IIP3 of 0 dBm, and IIP2 of 21 dBm at 16.4 GHz. The magnitude and phase errors between the I and Q channels are 1.34% and 0.6°, respectively. The dc power consumption of this I/Q mixer without output buffers is approximately 5 mW. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1516–1520, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25281

A subharmonic front-end in SiGe:C technology for 94-GHz imaging arrays

The design of a subharmonic downconverter for 94-GHz imaging arrays in SiGe:C technology is presented. A three-stage differential low-noise amplifier (LNA) with lumped matching networks is used together with a subharmonic mixer driven by a single-pole local-oscillator poly-phase network to form the front-end. The LNA yields 15 dB gain at 94 GHz, while the mixer provides 5 dB conversion gain over a 10 GHz IF bandwidth. The integrated downconverter provides 20 dB conversion gain at 94 GHz with an input 1-dB compression point of −31 dBm and has a current consumption of 45 mA at a 3.3 V supply voltage. The total required die area of the complete downconverter (excluding pad frame) is 0.1 mm, thus making it particularly suitable as a front-end in multi-channel receiver systems.

$Ka/Ku$-Band pHEMT Gilbert Mixers With Polyphase and Coupled-Line Quadrature Generators

In this paper, three kinds of Kalpha/Ku-band Gilbert mixers are demonstrated using 0.15- mum AlGaAs/InGaAs pseudomorphic high electron mobility transistor technology. Thanks to the semiinsulating GaAs substrate, microwave passive components have a low-loss feature, and polyphase filters work up to higher frequencies. Highly accurate tantalum-nitride thin-film resistors utilized in polyphase filters result in perfect quadrature operation. Therefore, our proposed single-sideband up-converter operates at 15 GHz with a 63-dB sideband rejection ratio, and another 34-GHz in-phase/quadrature (I/Q) subharmonic down-converter reaches <0.4-dB magnitude and < 1deg phase errors. More than 50-dB local oscillator (LO) leakage suppression is achieved in the I/Q subharmonic mixer. On the other hand, a 40-GHz stacked-LO subharmonic mixer with a novel compensation technique is also proposed and demonstrated to improve LO speed and reduce the amount of transistors, as compared to previous work.

A 9–31-GHz Subharmonic Passive Mixer in 90-nm CMOS Technology

A subharmonic down-conversion passive mixer is designed and fabricated in a 90-nm CMOS technology. It utilizes a single active device and operates in the LO source-pumped mode, i.e., the LO signal is applied to the source and the RF signal to the gate. When driven by an LO signal whose frequency is only half of the fundamental mixer, the mixer exhibits a conversion loss as low as 8-11 dB over a wide RF frequency range of 9-31GHz. This performance is superior to the mixer operating in the gate-pumped mode where the mixer shows a conversion loss of 12-15dB over an RF frequency range of 6.5-20 GHz. Moreover, this mixer can also operate with an LO signal whose frequency is only 1/3 of the fundamental one, and achieves a conversion loss of 12-15dB within an RF frequency range of 12-33 GHz. The IF signal is always extracted from the drain via a low-pass filter which supports an IF frequency range from DC to 2 GHz. These results, for the first time, demonstrate the feasibility of implementation of high-frequency wideband subharmonic passive mixers in a low-cost CMOS technology