Sturdy Multi-stage Noise Shaping Research Articles

A 10 MHz‐BW 85 dB‐SNDR 4th‐order sturdy MASH 2‐0 noise shaping SAR ADC with 2nd‐order gain‐error‐shaping technique

AbstractThe multi‐stage noise shaping (MASH) ΣΔ ADC has a good potential to achieve high‐order noise shaping (NS) and high resolution. However, it suffers from quantization noise leakage caused by the mismatch between the analogue NS filter and the digital cancellation filter, which greatly degrades the ADC performance. The sturdy MASH topology of the ΣΔ ADC can solve the leakage issue, but it cannot be implemented using the NS SAR ADC due to structural limitations. This paper proposes a sturdy MASH 2‐0 NS SAR to solve the noise leakage issue. The 4th‐order NS is achieved by only using a 2‐0 topology, which is hardware efficient. Instead of eliminating the first‐stage quantization error, the proposed sturdy MASH 2‐0 NS SAR shapes it, achieving better robustness to PVT variables. Furthermore, owing to the first‐stage 2nd‐order NS capability, the impairments of the residue amplifier, including the gain error and nonlinearity, are 2nd‐order shaped. The proposed 4th‐order sturdy MASH 2‐0 NS SAR is implemented in a 28 nm CMOS process, which achieves a SNDR of 85.6 dB and a SFDR of 101.3 dB with 10 MHz BW at OSR of 10, resulting in a Schreier FoM of 178.8 dB/179.4 dB (in SNDR/DR) with power consumption of 4.8 mW.

A Closed-Loop VCO-based 1-1 SMASH CT ΔΣ ADC Architecture

A novel closed-loop voltage-controlled oscillator (VCO)-based 1-1 sturdy multistage noise-shaping (SMASH) continuous-time ΔΣ ADC is presented in this paper. The proposed architecture uses VCOs as integrators and puts them in a closed loop to suppress the VCO nonlinearity. The multi-bit quantization is employed in the proposed architecture so that the requirement of a high over-sampling ratio (OSR) is relaxed while maintaining a high resolution. The architecture has been verified in MATLAB Simulink.

On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators

Sturdy multi-stage noise-shaping (SMASH) delta-sigma modulators (DSMs) achieve high-order noise-shaping while significantly alleviating the mismatch issue between analog and digital transfer functions. Based on the SMASH architecture, we propose a methodology of synthesizing its continuous-time (CT) architecture from its discrete-time (DT) counterpart by using loop-filter connections. The proposed methodology circumvents the necessity of a direct extraction of the quantization noise from the early stages, which is problematic for CT architectures with high sampling rate. Moreover, the proposed method allows to intuitively compensate the CT SMASH for the excess loop delay (ELD). Furthermore, an input feedforward path is introduced into the second stage to eliminate the STF peaking induced by the ELD. A 2–2 SMASH topology is analyzed as a case study to demonstrate the synthesis methodology. Besides, we present derivations for determining loop-filter coefficients. Simulation results confirm the efficacy of the synthesis methodology for the SMASH topology.

A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS

This article shows the design of a wideband 3-0 sturdy-multi-stage noise-shaping (SMASH) continuous-time (CT) incremental delta–sigma (I- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\Delta \Sigma }$ </tex-math></inline-formula> ) analog-to-digital converter (ADC). The two stages’ quantizers (QTZs) are implemented by a single re-configurable multibit (MB) asynchronous (A)SAR ADC. The digital-to-analog converter (DAC) nonlinearities are suppressed by reconfiguring the asynchronous successive-approximation register (ASAR) ADC from 2 to 5 b, and correspondingly, the DACs dynamically switch from 1.5- to 4-b tri-level outputs within each Nyquist conversion cycle. This results in a DAC-calibration-free MB operation. A two-tap FIR filter is implemented in the feedback DACs to reduce jitter requirements in the initial 1.5-b cycles. Through the design representation, a detailed fundamental comparison between an X-0 SMASH architecture and an X-order single-loop modulator is discussed. This discussion highlights the introduction of an efficient tri-level combination between the MSB and the LSBs of the ASAR QTZ. The resulting SMASH CT I- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\Delta \Sigma }$ </tex-math></inline-formula> modulator was fabricated in 28-nm CMOS technology with an active area of 0.125 mm2. It achieves 97-dB spurious-free dynamic range (SFDR) without calibration, 89-dB dynamic range (DR), and 81.2-dB SNDR in a 1-MHz bandwidth (BW). It consumes 3.6 mW from a single 0.9-V supply. The design shows very good robustness across different tested samples, supply variations, and across temperatures from −20 °C to 80 °C.

Correlated Dual-Loop Sturdy MASH Continuous-Time Delta-Sigma Modulators

This article presents a new multi-loop delta-sigma modulator (DSM) structure that combines the advantages of both the traditional multi-stage noise shaping (MASH) and sturdy MASH (SMASH) architectures. It removes the need for an explicit quantization error extraction digital-to-analog converter (DAC) typically required in multi-loop structures, which allows to eliminate the delay mismatch problem related to the intrinsic propagation delay of the first loop quantizer. The proposed architecture essentially uses the SMASH architecture as its core and has similar characteristics. However, it further simplifies the structure allowing to remove all the feedback DACs in the cascaded loop. The prototype DSM fabricated in a 65-nm process achieves signal-to-noise-and-distortion ratio (SNDR) and dynamic range (DR) of 73.4 and 78.3 dB, respectively, in an 18.75-MHz bandwidth. With 1.1/1.5-V (1.5 V for DAC) supply voltage, the prototype DSM consumes 17.85 mW at 600-MHz operating speed corresponding to a Walden and Schreier figure of merits (FOMs) of 124.1 fJ/conv-step and 168.6 dB (using DR result), respectively.

A CMOS Low-Power Noise Shaping-Enhanced SMASH ΣΔ Modulator

A discrete-time (DT) high-resolution and low-power sturdy multi-stage noise-shaping (SMASH) sigma-delta (ΣΔ) modulator is introduced. It proposes major solution for high-resolution applications relying on M-bit digital input-feedforward (DFF) technique which eliminates a power-hungry analog adder before the stage’s quantizer, decreases number of comparators for quantizer implementation and reduces the swing of the integrator’s output and a 2nd-order noise-coupling (NC) technique realized by few extra analog paths and enhances the noise shaping of the modulator without adding active blocks. The effectiveness of the introduced modulator is supported by the behavioral simulation and extensive mathematical analyses. The proposed modulator along with conventional one is simulated in a 0.18μm CMOS technology. The results indicate an outstanding improvement in dynamic range (DR) and resolution with less complexity.

Digital Mobile Fronthaul Based on Performance Enhanced Multi-Stage Noise-Shaping Delta-Sigma Modulator

A novel topology multi-stage noise-shaping (MASH) delta-sigma modulator is proposed for 20-km digital mobile fronthaul (MFH) in this article. In the proposed MASH structure, a newly designed feedback unit is combined with a traditional fourth-order sturdy MASH structure to enhance the noise-shaping capacity. The detailed comparison between the conventional fourth-order single delta-sigma modulator (SDSM) and the proposed new topology MASH is presented in a 512/1024 quadrature amplitude modulation (QAM) orthogonal frequency division multiplexing (OFDM) transmission system with the bandwidth of 1.125 GHz. The OFDM signal is quantized to two bits by SDSM/MASH analog-to-digital conversion (ADC), and this digitized signal is transmitted over 20-km single mode fiber (SMF) in 20-Gbaud 4-level pulse amplitude modulation (PAM4) intensity modulation direct detection (IM/DD) system. The signal to noise ratios (SNRs) of the retrieved OFDM signal utilizing the proposed new topology MASH and the fourth-order SDSM ADCs are 38.7dB and 34.5dB, respectively. In the case of 1024-QAM PAM4 system, the error vector magnitude (EVM) floors of the proposed new topology MASH and the conventional fourth-order SDSM schemes are 1.64% and 1.96% over 20-km SMF transmission at off-line digital signal processing (DSP) reception, and 1.2 dB receiver sensitivity improvement is achieved.

A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance

This article presents a dual-loop noise-coupling (NC)-assisted continuous-time (CT) sturdy multistage noise-shaping (SMASH) $\Delta \Sigma $ modulator (DSM), employing 1.5-bit/4-bit quantizers. The proposed SMASH can equivalently work as an overall fourth-order DSM with 4-bit internal quantization. The NC applied in this CT SMASH DSM whitens the 1.5-bit quantization noise (QN) and further reduces its in-band tone power, while a finite-impulse response (FIR) filter integrated into the outermost feedback path suppresses the out-of-band (OOB) noise power of the multibit digital-to-analog converter (DAC) input. Together, they avoid any linearization technique for the multibit DAC. Sampled at 1.2 GHz, the 28-nm CMOS experimental prototype measures a signal-to-noise-and-distortion ratio (SNDR) of 76.6 dB and a spurious-free dynamic range (SFDR) of 87.9 dB over a 50-MHz bandwidth (BW), consuming 29.2 mW from 1.2-V/1.5-V supplies and occupying an active area of 0.085 mm2. It exhibits a Schreier figure-of-merit (FoM) (SNDR) of 168.9 dB.

A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Resolution-Enhanced Sturdy MASH Delta–Sigma Modulator Using Source-Follower-Based Integrators

This paper presents a 2-2 discrete-time (DT) resolution-enhanced sturdy multi-stage noise-shaping (SMASH) delta–sigma modulator. It uses source-follower-based integrators to efficiently increase the operating speed of a DT modulator. A SMASH topology that consists of two second-order low-distortion feed-forward stages provides an enhanced linearity by reducing the sensitivity to the non-ideal gain and distortion of the proposed integrator. The resolution of the proposed SMASH architecture is improved by eliminating the first-stage quantization noise from the output. In order to reduce power and area of the modulator, one 5-bit feedback digital-to-analog converter is shared for both stages, and the number of comparators for a 4-bit quantizer in the second stage is reduced by scaling the signal swing range. The prototype delta–sigma modulator fabricated in a 65-nm CMOS process achieves a 75.8-dB dynamic range and 72.9-dB signal-to-noise-and-distortion ratio (SNDR) in a 20-MHz bandwidth. From a 1.2-V supply voltage operating at a 500-MHz clock frequency, the total power consumption of the prototype modulator is 20.4 mW, corresponding to a Walden and Schreier figure of merits of 141.3 fJ/conversion-step and 165.7 dB, respectively.

VCO‐based sturdy MASH ADC architecture

A new multistage 1-1 ΔΣ analogue-to-digital converter (ADC) architecture implemented only with voltage-controlled oscillators (VCOs) is introduced. A sturdy multistage noise-shaping (SMASH) configuration is used to avoid the need of either calibration circuitry or noise-cancellation filters. The digital nature of the VCO's output simplifies the implementation of the interconnection paths between stages, making unnecessary neither the use of multibit digital-to-analogue converters nor analogue subtraction elements. The basic operation of the architecture is shown at system level and the sensitivity to VCO's frequency mismatch is analysed. The proposed architecture has been validated through behavioural simulations.

A Continuous-Time Sturdy-MASH &lt;newline/&gt;&lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\Delta\Sigma$&lt;/tex&gt;&lt;/formula&gt; Modulator in 28 nm CMOS

This paper presents a practical way to achieve both wide signal bandwidth and high dynamic range in a continuous- time (CT) delta-sigma modulator. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function based on a sturdy multi-stage noise-shaping (SMASH) architecture. The proposed CT SMASH architecture has a much wider signal bandwidth which was limited in the discrete-time (DT) SMASH architecture due to the inherent sampling frequency limitation of DT implementation. Furthermore, the proposed CT SMASH architecture provides better quantization noise suppression by more completely canceling the quantization noise from the $1{\hbox {st}}$ -loop. The CT SMASH architecture is implemented with several efficient circuit techniques suitable for high operation speed. As a result, the prototype fabricated in 28 nm CMOS achieves DR of 85 dB, peak SNDR of 74.9 dB, SFDR of 89.3 dBc, and Schreier FOM of 172.9 dB over a 50 MHz bandwidth at a 1.8 GHz sampling frequency.

Resolution‐enhanced sturdy MASH delta–sigma modulator for wideband low‐voltage applications

A resolution-enhanced sturdy multi-stage noise shaping (MASH) delta–sigma modulator is presented. By employing the Leslie-Singh architecture in the first stage and an appropriate second stage digital filtering, the proposed structure could achieve much higher resolution [>80 dB signal-to-quantisation noise ratio] when compared with a traditional sturdy MASH, at a lower oversampling ratio (e.g. 8X). Interestingly, the mismatch between digital and analogue transfer functions is inherently shaped so that the structure is not sensitive to opamp finite gain error. Both these properties make the proposed structure suitable for wideband low-voltage applications. Behavioural simulations are presented to demonstrate the effectiveness of the proposed structure when compared with the prior art of its high performance delta–sigma counterparts.

Delay based noise cancelling sturdy MASH delta‐sigma modulator

A delay-based noise cancelling sturdy multi-stage noise shaping (MASH) structure that cancels the first-stage quantisation error is presented. Thus, a smaller number of bits can be used for the first-stage quantiser without degrading the overall performance. In addition, the proposed structure improves stability with respect to maximum applicable input by removing the first-stage quantisation error from the first loop.