Stuck-at Faults In Combinational Circuits Research Articles

On diagnosing multiple stuck-at faults using multiple and single fault simulation in combinational circuits

Diagnosing multiple stuck-at faults in combinational circuits using singleand multiple-fault simulation is proposed. The proposed method adds (removes) faults from a set of suspected faults depending on the result of multiple-fault simulation at a primary output agreeing (disagreeing) with the observed value. However, the faults that are added or removed from the set of suspected faults are determined using single-fault simulation. Diagnosis is carried out by repeated addition and removal of faults. The effectiveness of the diagnosis method is evaluated by experiments conducted on benchmark circuits and it is found to be substantially superior compared to the previous known solutions. The method proposed in this paper can be used as a powerful tool at the preprocessing stage of diagnosis in an electron-beam tester environment.

Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption

We show that the test generation problem for all single stuck-at faults in sequential circuits with internally balanced structures can be reduced into the test generation problem for single stuck-at faults in combinational circuits. In our previous work, we introduced internally balanced structures as a class of sequential circuits with the combinational test generation complexity. However, single stuck-at faults on some primary inputs, called separable primary inputs, corresponded to multiple stuck-at faults in a transformed combinational circuit. In this paper, we resolve this problem. We show how to generate a test sequence and identify undetectability for single stuck-at faults on separable primary inputs.

An exact solution to the minimum size test pattern problem

This article addresses the problem of test pattern generation for single stuck-at faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized. This problem has different applications in testing, including the identification of "don't care" conditions to be used in the synthesis of Built-In Self-Test (BIST) logic. The proposed solution is based on an integer linear programming (ILP) formulation which builds on an existing Propositional Satisfiability (SAT) model for test pattern generation. The resulting ILP formulation is linear on the size of the original SAT model for test generation, which is linear on the size of the circuit. Nevertheless, the resulting ILP instances represent complex optimization problems, that require dedicated ILP algorithms. Preliminary results on benchmark circuits validate the practical applicability of the test pattern minimization model and associated ILP algorithm.

Novel Test Generation Algorithm for Combination Circuits

It has been known for many years that combinational circuits have a Complete Test Set (CTS) which is capable of detecting all single and multiple faults. In this paper, we attempt to find CTS systematically. Our algorithm finds a test set which detects all single and multiple stuck-at faults in combinational circuits. This test set is obtained without probing internal nodes, using fault simulation or fault enumeration. It is shown that the test set is independent of logic circuit structure and dependent to the mapping function, number of inputs, outputs, and fanout stems. An upper-bound and lower-bound figures for the number of test vectors required to obtain 100% fault coverage are provided. This number is a small fraction of the entire solution space. A number of recommendations are made to improve the testability of a logic circuit.

NOVEL TEST GENERATION ALGORITHM FOR COMBINATION CIRCUITS

It has been known for many years that combinational circuits have a Complete Test Set (CTS) which is capable of detecting all single and multiple faults. In this paper, we attempt to find CTS systematically. Our algorithm finds a test set which detects all single and multiple stuck-at faults in combinational circuits. This test set is obtained without probing internal nodes, using fault simulation or fault enumeration. It is shown that the test set is independent of logic circuit structure and dependent to the mapping function, number of inputs, outputs, and fanout stems. An upper-bound and lower-bound figures for the number of test vectors required to obtain 100% fault coverage are provided. This number is a small fraction of the entire solution space. A number of recommendations are made to improve the testability of a logic circuit.

IDDQ Detectable Bridges in Combinational CMOS Circuits

Undetectable stuck-at faults in combinational circuits are related to the existence of logic redundancy (s-redundancy). Similarly, logically equivalent nodes may cause some bridging faults to become undetectable by IDDQ testing. An efficient method for the identification and removal of such functionally equivalent nodes (f-redundant nodes) in combinational circuits is presented. OBDD graphs are used to identify the functional equivalence of candidate to f-redundancy nodes. An f-redundancy removal algorithm based on circuit transformations to improve bridging fault testability, is also proposed. The efficiency of the identification and removal of f-redundancy has been evaluated on a set of benchmark circuits.

Diagnostic simulation of stuck-at faults in combinational circuits

Two faults are said to be equivalent, with respect to a test set τ, iff they cannot be distinguished by any test in τ. The sizes of the corresponding equivalence classes of faults are used as a basis for comparing the diagnostic capability of two given test sets. A novel algorithm, called “multiway list splitting,” for computing the Equivalence Classes of stuck-at faults, in combinational (full scan) circuits, with respect to a given test set is presented. Experimental results presented show the algorithm to be more efficient than previously known algorithms based on decision diagrams and diagnosibility matrix.

On the generation of test patterns for multiple faults

This article presents a new method to generate test patterns for multiple stuck-at faults in combinational circuits. We assume the presence of all multiple faults of all multiplicities and we do not resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. New line and gate models are introduced to handle multiple fault effect propagation through the circuits. The method tries to generate test conditions that propagate the effect of the target fault to primary outputs. When these conditions are fulfilled, the input vector is a test for the target fault and it is guaranteed that all multiple faults of all multiplicities containing the target fault as component are also detected. The method uses similar techniques to those in FAN and SOCRATES algorithms to guide the search part of the algorithm, and includes several new heuristics to enhance the performance and fault detection capability. Experiments performed on the ISCAS'85 benchmark circuits show that test sets for multiple faults can be generated with high fault coverage and a reasonable increase in cost over test generation for single stuck-at faults.

A method of diagnosing single stuck-at faults in combinational circuits

A method of diagnosing single stuck-at faults in combinational circuits

Test pattern generation using Boolean satisfiability

The author describes the Boolean satisfiability method for generating test patterns for single stuck-at faults in combinational circuits. This new method generates test patterns in two steps: first, it constructs a formula expressing the Boolean difference between the unfaulted and faulted circuits, and second, it applies a Boolean satisfiability algorithm to the resulting formula. This approach differs from previous methods now in use, which search the circuit structure directly instead of constructing a formula from it. The new method is general and effective. It allows for the addition of heuristics used by structural search methods, and it has produced excellent results on popular test pattern generation benchmarks. >

Method of diagnosing multiple stuck-at-faults in combinational circuits

To reduce VLSI turnaround time and cost, an efficient fault diagnosis method must be developed. Electron-beam probing, which allows observation of the signal values within a chip, is one of the promising approaches for fault diagnosis. However, it is strongly desired that the number of probes be reduced; otherwise, a great deal of effort results. The electron-beam probing, guided by deduction based on implications of internal signal values [6], is considered one of the effective solutions to this problem. Here this idea is built upon by adding preprocessing to further reduce the number of probes and postprocessing to improve the diagnosis resolution. The method proposed efficiently diagnoses multiple stuck-at faults in combinational circuits. Using computational experiments it is also shown that almost all of the faults are diagnosed by probing about 15 percent of the nets when test patterns for detecting single stuck-at faults are used.

Complete test generation method for all stuck-at faults in combinational circuits

In combinational logic circuits the generation of complete fault detection test sets requires the determination of the complete test sets of all possible stuck-at faults. In this study, an efficient procedure is developed for finding all the complete test sets of all possible single stuck-at faults in a combinational circuit. The developed procedure primarily uses the properties of logic gates. An example is solved by the use of the developed procedure.