Structured Low-density Parity-check Codes Research Articles

Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes

The error floor phenomenon, associated with iterative decoders, is one of the most significant limitations to the applications of low-density parity-check (LDPC) codes. A variety of techniques from code design to decoder implementation have been proposed to address the error floor problem, among which post-processors have shown to be both effective and implementation-friendly. In this paper, we take the inspiration from simulated annealing to generalize the post-processor design using three methods: quenching, extended heating, and focused heating, each of which targets a different error structure. The resulting post-processor is demonstrated to lower the error floors by two orders of magnitude for two structured code examples, a (2209, 1978) array LDPC code and a (1944, 1620) LDPC code used by the IEEE 802.11n standard. The post-processor can be integrated with a belief-propagation decoder with minimal overhead. The post-processor design is equally applicable to other structured LDPC codes.

High‐throughput Bit Flipping decoder for structured LDPC codes

Low-density parity-check (LDPC) codes are predominantly used in many energy scavenging devices, data centres, and communication devices. In this work, the authors propose a high-throughput parallel bit-flipping (BF) decoder using multithreshold BF algorithm. The decoder is endowed with features including low interconnect complexity, simpler computations, and high throughput. The decoder has been synthesised in 65 nm technology for (273, 191) and (1023, 781) finite-geometry LDPC (FG-LDPC) codes. These decoders require an area of 0 . 1 and 0 . 45 mm 2 , and they achieve an average throughput of 147 . 57 and 268 . 5 Gbps and energy efficiency of 0 . 92 and 0 . 91 pJ/bit for (273, 191) and (1023, 781) FG-LDPC codes, respectively. Compared to the state-of-the-art design, the proposed designs offer 4 . 5 times higher normalised throughput.

Design of LDPC Codes Based on Multipath EMD Strategies for Progressive Edge Growth

Low-density parity-check (LDPC) codes are capable of achieving excellent performance and provide a useful alternative for the high-performance applications. However, at medium to high signal-to-noise ratios, an observable error floor arises from the loss of independence of messages passed under iterative graph-based decoding. In this paper, the error floor performance of the short block length codes is improved by the use of a novel candidate selection metric in code graph construction. The proposed multipath extrinsic message degree (EMD) approach avoids harmful structures in the graph by evaluating certain properties of the cycles introduced in each edge placement. We present multipath EMD-based designs for several structured LDPC codes, including quasi-cyclic and the irregular repeat accumulate codes. In addition, an extended class of the diversity-achieving codes on the challenging block fading channel is proposed and considered with the multipath EMD design. This combined approach is demonstrated to provide the gains in decoder convergence and error rate performance. A simulation study evaluates the performance of the proposed and existing state-of-the-art methods.

Security gap analysis of some LDPC coded transmission schemes over the flat and fast fading Gaussian wire-tap channels

It is known that the error rate can be used as a measure of reliability and security over the wire-tap channel when practical, finite length codes are used for transmission, and the security gap is an error rate based metric able to jointly treat these two aspects. In this paper, we consider several low-density parity-check (LDPC) coded transmissions, which represent the state of the art for transmissions over the wire-tap channel and we assess and compare their security gap performance. We consider two kinds of wire-tap channels: the flat and the fast fading wire-tap channels with additive white Gaussian noise. As a reference, we use the progressive edge growth (PEG) algorithm for the design of unstructured LDPC codes and compare its performance with that of four approaches for designing structured LDPC codes. We analyze both systematic and non-systematic transmissions and show that some structured code design techniques are able to achieve comparable or even better performance than the PEG algorithm over the considered channels, while taking advantage of their simpler encoding and decoding procedures.

A Novel Construction Approach of Irregular LDPC Codes Based on QC Structure and Zigzag Pattern

This paper presents a novel construction method of irregular Low-density parity-check (LDPC)codes based on Quasi-cyclic (QC) structure and zigzag pattern. By using the proposed method, a class of irregularand highly structured LDPC codes can be designed withthe advantages of low storage requirement and linear timeencoding complexity. The constructed codes are called Irregular repeat-accumulate like (IRA-like) codes since theirparity-check matrices are similar with those of IRA codes,which all contain a sparse zigzag pattern submatrix. Theleft part of the parity-check matrix of IRA-like codes is akind of circulant permutation matrix. A best-effort analyzing method for optimizing the cycle structure of IRAlike codes is presented. We further details the proper constraints for avoiding short cycles and low-weight codewords. Simulation results show that the proposed IRA-likecodes have low encoding complexity, good iterative decoding performance and flexible choice of code parameters.

Multi-Threshold Bit Flipping Algorithm for Decoding Structured LDPC Codes

A novel bit-flipping (BF) decoding algorithm is proposed for structured low-density parity-check (LDPC) codes. The proposed BF algorithm which is called multi-threshold bit-flipping (MTBF) algorithm, flips multiple bits by using multiple thresholds at each iteration. It only requires some real operations before iterations and requires only logical operations during the iterations. The MTBF algorithm has lower complexity than the weighted bit-flipping algorithm and its modifications. Simulations show that the proposed algorithm has fast convergence speed and good performance.

Nonbinary LDPC Codes on Cages: Structural Property and Code Optimization

A (v,g)-cage is a (not necessarily unique) smallest v-regular graph of girth g. On such a graph, a nonbinary (2,v)-regular low-density parity-check (LDPC) code can be defined such that the Tanner graph has girth 2g and the code length achieves the minimum possible. In this paper, we focus on two aspects of this class of codes, structural property and code optimization. We find that, in addition to those found previously, many cages can be used to construct structured LDPC codes. We show that all cages with even girth can be structured as protograph-based codes, many of which have block-circulant Tanner graphs. We also find that four cages with odd girth can be structured as protograph-based codes with block-circulant Tanner graphs. For code optimization, we develop an ontology-based approach. All possible inter-connected cycle patterns that lead to low symbol-weight codewords are identified to put together the ontology. By doing so, it becomes handleable to estimate and optimize distance spectrum of equivalent binary image codes. We further analyze some known codes from the Consultative Committee for Space Data Systems recommendation and design several new codes. Numerical results show that these codes have reasonably good minimum bit distance and perform well under iterative decoding.

A Survey on Protograph LDPC Codes and Their Applications

Low-density parity-check (LDPC) codes have attracted much attention over the past two decades since they can asymptotically approach the Shannon capacity in a variety of data transmission and storage scenarios. As a type of promising structured LDPC codes, the protograph LDPC codes not only inherit the advantage of conventional LDPC codes, i.e., excellent error performance, but also possess simple representations to realize fast encoding and efficient decoding. This paper provides a comprehensive survey on the state-of-the-art in protograph LDPC code design and analysis for different channel conditions, including the additive white Gaussian noise (AWGN) channels, fading channels, partial response (PR) channels, and Poisson pulse-position modulation (PPM) channels. Moreover, the applications of protograph LDPC codes to joint source-and-channel coding (JSCC) and joint channel-and-physical-layer-network coding (JCPNC) are reviewed and studied. In particular, we focus our attention on the encoding design and assume the decoder is implemented by the belief propagation (BP) algorithm. Hopefully, this survey may facilitate research in this area.

Asymptotic Distribution of Absorbing Sets and Fully Absorbing Sets for Regular Sparse Code Ensembles

It is well recognized that low-density parity-check (LDPC) codes can suffer from an error floor when decoded iteratively. This performance degradation is often attributed to the class of objects known as trapping sets. Past work has focused on characterizing the distribution of trapping sets for a variety of code ensembles, including regular, irregular and structured LDPC codes. As a subset of the trapping set collection, there exists a class of graphical structures called the absorbing sets. An absorbing set is a combinatorially-defined object; in particular a fully absorbing set is stable under bit-flipping decoding. By construction, there can exist trapping sets that are not stable under such a decoder. As a result, for finite-precision, iterative decoding algorithms used over additive channels, absorbing sets can describe decoding errors more accurately than the broader class of trapping sets. In this paper, we compute the normalized logarithmic asymptotic distributions of absorbing sets and fully absorbing sets, including elementary (fully) absorbing sets. The calculations are based on the trapping set enumeration method proposed by Milenkovic, Soljanin, and Whiting in [1]. We compare distributions of absorbing and trapping sets for representative code parameters of interest, and quantify the (lack of) discrepancies between the two. Good absorbing set properties are implied for known structured LDPC codes, including repeat accumulate codes and protograph-based constructions. Establishing the distribution of fully absorbing sets (especially when the discrepancy with the trapping set distribution is significant) allows one to further refine the estimates of the error rates under bit-flipping and related decoders.

Joint Shortening and Puncturing Optimization for Structured LDPC Codes

The demand for flexible broadband wireless services makes the pruning technique, including both shortening and puncturing, an indispensable component of error correcting codes. The analysis of the pruning process for structured low-density parity-check (LDPC) codes can be considerably simplified with their equivalent representations through base-matrices or protographs. In this letter, we evaluate the thresholds of the pruned base-matrices by using protograph based on extrinsic information transfer (PEXIT). We also provide an efficient method to optimize the pruning patterns, which can significantly improve the thresholds of both the full-length patterns and the sub-patterns. Numerical results show that the structured LDPC codes pruned by the improved patterns outperform those with the existing patterns.

On the Construction of Structured LDPC Codes Free of Small Trapping Sets

We present a method to construct low-density parity-check (LDPC) codes with low error floors on the binary symmetric channel. Codes are constructed so that their Tanner graphs are free of certain small trapping sets. These trapping sets are selected from the trapping set ontology for the Gallager A/B decoder. They are selected based on their relative harmfulness for a given decoding algorithm. We evaluate the relative harmfulness of different trapping sets for the sum-product algorithm by using the topological relations among them and by analyzing the decoding failures on one trapping set in the presence or absence of other trapping sets. We apply this method to construct structured LDPC codes. To facilitate the discussion, we give a new description of structured LDPC codes whose parity-check matrices are arrays of permutation matrices. This description uses Latin squares to define a set of permutation matrices that have disjoint support and to derive a simple necessary and sufficient condition for the Tanner graph of a code to be free of four cycles.

Modeling of 2-D Magnetic Recording and a Comparison of Data Detection Schemes

Two-dimensional magnetic recording (TDMR) together with shingled magnetic recording (SMR) are technologies proposed to extend the life of conventional granular magnetic recording. The grain flipping probability (GFP) model has been proposed to mimic the performance of micromagnetic ( μ-mag) simulations for the purpose of signal reproduction. Other work in TDMR includes the proposal of a Gaussian mixture model (GMM) that produces improved likelihood information at the output of the detector, combined with low density parity check (LDPC) codes. The contribution of this paper is threefold. First, we aim to simulate a TDMR/SMR recording system with the GFP model, both with and without the GMM detector, and with various random and structured LDPC codes, of both 4 k and 16 k block lengths, to determine areal densities that might be achieved. Second, we perform a comparison of the various model order reduced (MOR) GFP implementations to compare the effect of writing with various factors taken out of the picture. Third, we perform a validation of the GFP model and the setup as a whole, by running the system with a parameter set close to that of conventional recording. The results of these experiments give an assurance of the validity of our model, give an indication of the expected density that might be achieved in a TDMR/SMR system, and give a direction for which parameter(s) in magnetic recording systems might be optimized to yield the most gain.

VLSI Design for Low-Density Parity-Check Code Decoding

Low-Density Parity-check (LDPC) code, being one of the most promising near-Shannon limit error correction codes (ECCs) in practice, has attracted tremendous attention in both academia and industry since its rediscovery in middle 1990's. Owning excellent coding gain, LDPC code also has very low error floor, and inherent parallizable decoding schemes. Compared to other ECCs such as Turbo codes, BCH codes and RS codes, LDPC code has many more varieties in code construction, which result in various optimum decoding architectures associated with different structures of the parity-check matrix. In this work, we first provide an overview of typical LDPC code structures and commonly-used LDPC decoding algorithms. We then discuss efficient VLSI architectures for random-like codes and structured LDPC codes. We further present layered decoding schemes and corresponding VLSI architectures. Finally we briefly address non-binary LDPC decoding and multi-rate LDPC decoder design.

Structured LDPC Codes to Reduce Pseudo Cycles for Turbo Equalization in Perpendicular Magnetic Recording

Low-density parity-check (LDPC) codes are typically designed to avoid the length-4 cycles to ensure acceptable levels of performance. However, the turbo equalization, which relies on an interaction between an inner code such as an LDPC code and a soft-output Viterbi algorithm (SOVA) detector, exhibits a performance degradation due to the pseudo cycles. In this paper, we propose an interleaved modified array code (IMAC) that can reduce the number of pseudo cycles, hence, improving the gains from the iterative processing technique. The modification is made on the existing array-based LDPC codes named modified array codes (MAC) by introducing an additional interleaving matrix to the parity-check matrix. Simulation results on the perpendicular magnetic recording channels (PMRC) demonstrate that the IMAC outperforms both the MAC and the previously proposed random interleave array (RIA) codes for the partial-response targets under consideration. In addition, a subblock-based encoder design is proposed to reduce the encoding complexity of the IMAC and when compared with the RIA code, the IMAC exhibits a lower encoding complexity, and still maintains a comparable level of the decoding complexity.

Analysis of Absorbing Sets and Fully Absorbing Sets of Array-Based LDPC Codes

The class of low-density parity-check (LDPC) codes is attractive, since such codes can be decoded using practical message-passing algorithms, and their performance is known to approach the Shannon limits for suitably large block lengths. For the intermediate block lengths relevant in applications, however, many LDPC codes exhibit a so-called ?error floor,? corresponding to a significant flattening in the curve that relates signal-to-noise ratio (SNR) to the bit-error rate (BER) level. Previous work has linked this behavior to combinatorial substructures within the Tanner graph associated with an LDPC code, known as (fully) absorbing sets. These fully absorbing sets correspond to a particular type of near-codewords or trapping sets that are stable under bit-flipping operations, and exert the dominant effect on the low BER behavior of structured LDPC codes. This paper provides a detailed theoretical analysis of these (fully) absorbing sets for the class of Cp, ? array-based LDPC codes, including the characterization of all minimal (fully) absorbing sets for the array-based LDPC codes for ? = 2,3,4, and moreover, it provides the development of techniques to enumerate them exactly. Theoretical results of this type provide a foundation for predicting and extrapolating the error floor behavior of LDPC codes.

Predicting error floors of structured LDPC codes: deterministic bounds and estimates

The error-correcting performance of low-density parity check (LDPC) codes, when decoded using practical iterative decoding algorithms, is known to be close to Shannon limits for codes with suitably large blocklengths. A substantial limitation to the use of finite-length LDPC codes is the presence of an error floor in the low frame error rate (FER) region. This paper develops a deterministic method of predicting error floors, based on high signal-to-noise ratio (SNR) asymptotics, applied to absorbing sets within structured LDPC codes. The approach is illustrated using a class of array-based LDPC codes, taken as exemplars of high-performance structured LDPC codes. The results are in very good agreement with a stochastic method based on importance sampling which, in turn, matches the hardware-based experimental results. The importance sampling scheme uses a mean-shifted version of the original Gaussian density, appropriately centered between a codeword and a dominant absorbing set, to produce an unbiased estimator of the FER with substantial computational savings over a standard Monte Carlo estimator. Our deterministic estimates are guaranteed to be a lower bound to the error probability in the high SNR regime, and extend the prediction of the error probability to as low as 10-30. By adopting a channel-independent viewpoint, the usefulness of these results is demonstrated for both the standard Gaussian channel and a channel with mixture noise.

Design of low-rate irregular LDPC codes using trellis search

A simple design method using trellis search is proposed for good low-density parity-check (LDPC) codes with relatively low code rates. By applying a trellis search technique to the design of a pre-assigned part of the parity-check matrix that allows a simple encoding, we improve the distribution of cycles formed by the entries contained in the parity-check part of the parity-check matrix. In addition, we extend the proposed algorithm to a class of structured LDPC codes, which have been recently preferred in many practical applications. Simulation results show that the codes designed by the proposed method outperform those constructed by conventionally used greedy design algorithms.

Structured LDPC Codes over Integer Residue Rings

This paper presents a new class of low-density parity-check (LDPC) codes over represented by regular, structured Tanner graphs. These graphs are constructed using Latin squares defined over a multiplicative group of a Galois ring, rather than a finite field. Our approach yields codes for a wide range of code rates and more importantly, codes whose minimum pseudocodeword weights equal their minimum Hamming distances. Simulation studies show that these structured codes, when transmitted using matched signal sets over an additive-white-Gaussian-noise channel, can outperform their random counterparts of similar length and rate.

Use of Low-Density Parity-Check Codes for Dominant Error Events Detection and $k$-Constraint Enforcement

In this paper, we propose to leverage the simple and explicit parity checks inherent in low-density parity-check (LDPC) codes to detect dominant error events without code rate penalty. This is enabled by enforcing a very weak constraint on the LDPC code parity check matrix structure. Such a constraint can be readily satisfied by most structured LDPC codes reported in the open literature, such as quasi-cyclic (QC) LDPC codes. Moreover, this zero-redundancy dominant error events detection can be extended to handle the bit errors that occur when deliberate bit-flipping is used to enforce -constraints. We have demonstrated the effectiveness of the proposed method in computer simulations.

Multi-size circular shifting networks for decoders of structured LDPC codes

The need for circularly shifting an array of data is a distinguishing feature of decoders for structured low-density parity-check (LDPC) code, as a result of an efficient trade-off between performance and parallelisation of the elaborations, or throughput. Since the decoder must typically cope with blocks of data with different size, described is an efficient architecture of a reconfigurable multi-size circular shifting network, used to circularly shift an array with arbitrary size.