Abstract To continuously increase storage density, an asymmetrical 3D NAND memory architecture has recently been proposed that eliminates the need for dummy memory holes during the fabrication of separate drain-side select gates (SGD). However, this innovation results in an incomplete On-Pitch SGD (OPS) structure, which leads to significant threshold voltage (V th) tail deterioration and downshift. In this work, the degree of incompleteness and the influence of neighbor SGD interference (NSI) are studied based on 3D TCAD simulation. It is found that the V th distribution shifts more with higher neighbor SGD bias, especially in certain imperfect structures. The nonlinear structural dependence and sensitive NSI are due to the asymmetric shielding potential, which leads to electron aggregation and the formation of abnormal weakly-on region, thus deteriorating the V th distribution of OPS. Furthermore, a neighbor SGD bias scheme is demonstrated to improve the V th distribution and suppress the OPS V th downshift during read operation.
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