Stringent Hardware Constraints Research Articles

Layer-Wise Compressive Training for Convolutional Neural Networks

Convolutional Neural Networks (CNNs) are brain-inspired computational models designed to recognize patterns. Recent advances demonstrate that CNNs are able to achieve, and often exceed, human capabilities in many application domains. Made of several millions of parameters, even the simplest CNN shows large model size. This characteristic is a serious concern for the deployment on resource-constrained embedded-systems, where compression stages are needed to meet the stringent hardware constraints. In this paper, we introduce a novel accuracy-driven compressive training algorithm. It consists of a two-stage flow: first, layers are sorted by means of heuristic rules according to their significance; second, a modified stochastic gradient descent optimization is applied on less significant layers such that their representation is collapsed into a constrained subspace. Experimental results demonstrate that our approach achieves remarkable compression rates with low accuracy loss (<1%).

Making Wireless Body Area Networks Robust Under Cross-Technology Interference

Wireless body area networks (BANs) demand high-quality service. However, as BANs will be widely deployed in densely populated areas, they inevitably face RF cross-technology interference (CTI) from non-protocol-compliant wireless devices operating in the same spectrum range. The main challenges to defending against such a strong CTI come from the scarcity of spectrum resources, the uncertainty of the CTI sources and BAN channel status, and the stringent hardware constraints. In this paper, we first experimentally characterize the adverse effect on BAN reliability caused by the non-protocol-compliant CTI. Then, we formulate a joint routing and power control (JRPC) problem, which aims at minimizing energy consumption under strong CTI while satisfying node reachability and delay constraints. We reformulate our problem into a mixed integer linear programing problem and then derive the optimal results through IBM’s CPLEX. A practical protocol, including a heuristic JRPC algorithm, is then proposed, in which we address the challenge of fast link-quality measurement by proposing a passive link-quality estimation and prediction method. Through experiments and simulations, we show that our protocol can assure the robustness of BAN even when the CTI sources are in very close vicinity, using a small amount of energy on commercial-off-the-shelf sensor devices.

An agile development methodology applied to embedded control software under stringent hardware constraints

In recent years, discrete control systems play an important role in the development and advancement of modern civilization and technology. Practically every aspect of our life is affected by some type of control systems. This kind of system maybe classified as an embedded real-time system and requires rigorous methodologies to develop the software that is under stringent hardware constraints. Therefore, the proposed development methodology adapts agile principles and patterns in order to build embedded control systems focusing on the issues related to the system's constraints and safety. Strong unit testing is the foundation of the proposed methodology for ensuring timeliness and correctness. Moreover, platform-based design approach is used to balance costs and time-to-market in view of performance and functionality constraints. We conclude that the proposed methodology reduces significantly the design time and cost as well as leads to better software modularity and reliability.